Allegro X PCB Editor - Recent Threads

Can we highlight multiple vias by using xy cordinates at a time in allegro

BC202603263145 — Fri, 17 Jul 2026 11:07:10 GMT

I have a list of vias with its XY locations. I need to highlight all these vias at once. How would I do that in Allegro?

SPB 16.6 BASE RELEASE NOT FOUND

KB202607102640 — Sat, 11 Jul 2026 04:40:19 GMT

Hello everyone,

I have a legitimate Cadence OrCAD/SPB 16.6 standalone perpetual license purchased directly from Cadence.

However, the installation DVD I have contains only:

HotFix_SPB16.60.010_wint_1of1.exe (ISR10)
My license (.lic) file
The installation guide (PDF)

There is no SPB/OrCAD 16.6 Base Release installer (setup.exe, Disk1, Disk2, etc.).

When I run the HotFix installer, I receive the following error:

SPB 16.6 Base Release Not Found

I understand that the HotFix requires the Base Release to already be installed, but I do not have the Base Release installation media.

My questions are:

Is the SPB/OrCAD 16.6 Base Release still available for customers with a standalone perpetual license?
Can it still be downloaded from the Cadence Support Portal?
If not, what is the recommended way to obtain the Base Release installer?
Has anyone else encountered this situation where only the ISR DVD was provided?

I would appreciate any guidance from Cadence staff or users who have dealt with this issue.

Thank you.

RE: SPB 16.6 BASE RELEASE NOT FOUND

John T — Fri, 17 Jul 2026 08:41:47 GMT

Hi KB - I have no reply from you yet... i see you posted the same question twice on the community it seems Hope you can find this friend request. You should have received a personal email about the request also to notify you. Hope this message finds you well,

From Challenges to Solution: Interactive 3DX Canvas Session - Join us on July 22nd

Renu Vibha — Thu, 16 Jul 2026 11:22:00 GMT

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Board Outline and Cutouts Not Showing Up for PCB Manufacturer

SB202607126042 — Sun, 12 Jul 2026 19:25:11 GMT

Hi everyone,

I'm facing a problem after exporting my Gerber files. My PCB outline and cutouts are not showing up for the manufacturer.

I'm using JLCPCB, and when I use their DFM tool to perform the final verification, everything appears correctly except the board outline and cutouts.

The board outline was created in Board Geometry > Design_Outline, and the cutouts were created in Board Geometry > Cutout. Both layers are included in my artwork and are being exported to the Gerber files that I send to the manufacturer.

Am I missing something? This is my first project using Cadence PCB software.

RE: Board Outline and Cutouts Not Showing Up for PCB Manufacturer

excellon1 — Thu, 16 Jul 2026 00:13:04 GMT

Excellent. glad you got it to work.

BTW NCROUTE_PATH also shows up in the 3d view of your board, so you can get a nice visual if needed. The added advantage of ncroute_path is that one can generate a route file from it, similar to how NC drill works.

All the best.

RE: Board Outline and Cutouts Not Showing Up for PCB Manufacturer

SB202607126042 — Wed, 15 Jul 2026 23:12:49 GMT

Hello,

Yes, I needed to make a cut (slot) between some components to ensure electrical isolation between them.

I actually found the solution today. Instead of using BOARD GEOMETRY / CUTOUT, I used BOARD GEOMETRY / NCROUTE_PATH and drew the slot using thick lines. That worked perfectly.

😀

I also had to generate the board outline in a separate Gerber file containing only the BOARD GEOMETRY / DESIGN_OUTLINE layer. Otherwise, the JLCPCB DFM tool couldn't recognize the board outline correctly.

Thanks for your help!

RE: Board Outline and Cutouts Not Showing Up for PCB Manufacturer

excellon1 — Wed, 15 Jul 2026 04:35:39 GMT

HI SB.

I had not used the JL PCB DFM tool but for gerber creation the following might be of help.

On your layer structure some board house prefer that the physical design outline exists on all layers of your design, so for example assuming the top layer that would be.

TOP
board geometry/design_outline
ETCH/TOP
PIN/TOP
VIA CLASS/TOP

This can help them when creating a panel as all layers will be aligned using the physical board outline.
"Basically your design_outline is incorporated into every gerber layer you export"

Note: typically a design will use a Board Origin, this is used as a reference point, typically bottom left of the board. So go to setup change drawing origin so as to set that on your board. More than likely you have this in place already.

In addition to the gerber export, it may be worth checking the gerber format. On the general Parameters tab check

Device Type - Gerber RS274X
Suppress - Leading Zeros "Checked", Equal Coordinates "Checked"
Format - Typically allegro sizes this but Integer places - 2, Decimal places 5 work fine
Output Units - Inches or Millimeters, Depends on design.

You mentioned a cutout, do you mean that a certain part of the board will be physically milled out or something else ?.

Best Regards.

RE: Add Collision Detection and ability to XY snap to faces to 3Dx

JM20241029170 — Tue, 14 Jul 2026 15:17:28 GMT

I appreciate you taking the time to replicate and pass along the issue!

Add Collision Detection and ability to XY snap to faces to 3Dx

JM20241029170 — Tue, 07 Jul 2026 16:18:59 GMT

A critical feature missing from 3Dx is collision detection. The new 3D drc is good for internal designs, but I can't determine if mechanical imported models collide with the design. This is how I check multi-board assemblies, by exporting each board to a STEP then importing them into one canvas to assemble and check for collisions. Also, 3Dx doesn't allow me to select faces on component bodies (like a connector) to snap with XY like on the old 3D canvas...this makes assembly impossible besides doing it by hand!

I can't use the old 3D canvas since it has recently become unstable when importing 3D models, so forced to use new 3Dx that is missing core features.

RE: Add Collision Detection and ability to XY snap to faces to 3Dx

steve — Tue, 14 Jul 2026 08:11:54 GMT

There are now DRC markers in the 3dx canvas that show where the clashes are so make sure they are turned on. For the face mapping, I managed to reproduce this and passed this onto the Cadence R & D team for them to hopefully fix at some stage.

RE: Board Outline and Cutouts Not Showing Up for PCB Manufacturer

SB202607126042 — Mon, 13 Jul 2026 23:21:05 GMT

Hi Juan,

Thanks for answering.

I've attached a screenshot of my Artwork window. For now, I decided to place BOARD GEOMETRY / DESIGN_OUTLINE and BOARD GEOMETRY / CUTOUT into separate Gerber files (BOARD.art and CUTOUT.art) to see if generating two files would solve the problem.

Previously, both layers were included in the same BOARD.art file. When they were exported together, neither the board outline nor the cutouts were recognized by the manufacturer's DFM tool. However, after separating them, at least the board outline is now recognized.

I'm also not sure if I'm creating the cutouts correctly. At the moment, I'm simply drawing a closed shape on the BOARD GEOMETRY / CUTOUT subclass.

Back when I was using Altium Designer, I would draw a line (or another closed shape) and the convert that entity into a board cutout. I'm not sure if the workflow is different in Cadence PCB Editor.

RE: Board Outline and Cutouts Not Showing Up for PCB Manufacturer

JuanCR — Mon, 13 Jul 2026 16:45:02 GMT

Hi!

Open Export > Artwork.
In the Artwork Control Form, look at your Outline film.
Expand the film (click the + next to the film name) and verify that BOARD GEOMETRY / DESIGN_OUTLINE and BOARD GEOMETRY / CUTOUT are actually listed there.
If they are missing, right-click the film name, select Add, and pick those layers from the class/subclass list.
Ensure the Undefined line width in the Artwork Control Form is set to a small positive value (e.g., 0.1) to ensure zero-width lines are rendered.

Please post a screenshot of how your Export > Artwork form looks like.

RE: SPB 16.6 BASE RELEASE NOT FOUND

John T — Mon, 13 Jul 2026 14:33:38 GMT

Hi KB, my name is John from the Cadence support team. The old tools are not technically supported and designed for 32bit OS. The best way to get this is to open a case with us so we can work with you on this. I have sent you a community friend request so we can discuss further and I will do my best for you.

RE: Board Geometry / DESIGN_OUTLINE vs. OUTLINE And What Are the Real-World Implications?

Electro Node — Fri, 10 Jul 2026 16:58:48 GMT

Hello steve,

Thank you for the explanation and for pointing me to the ParSysEDA video. The distinction between the legacy OUTLINE subclass and the newer DESIGN_OUTLINE/CUTOUT subclasses, particularly the requirement for closed shapes and the implications for MCAD integration, export data, and 3DX Canvas, is very helpful. appreciate the insight and will definitely explore the video for a deeper understanding

Best Regards,

Board Geometry / DESIGN_OUTLINE vs. OUTLINE And What Are the Real-World Implications?

Electro Node — Wed, 08 Jul 2026 15:01:34 GMT

Hi everyone,

I've always been a bit confused about the difference between Board Geometry / DESIGN_OUTLINE and the legacy Board Geometry / OUTLINE subclasses in Allegro X PCB Editor.

If the board boundary is defined using Board Geometry / OUTLINE instead of DESIGN_OUTLINE, could that cause any issues during manufacturing, fabrication outputs, MCAD exchange, or other downstream processes? Or is it still generally acceptable in production designs?

I'd love to hear how others are handling this in their workflows. Have you encountered any problems, benefits, or best practices related to using one versus the other? Looking forward to learning from your experiences!

Best Regards,

RE: Board Geometry / DESIGN_OUTLINE vs. OUTLINE And What Are the Real-World Implications?

steve — Thu, 09 Jul 2026 10:53:45 GMT

Take a look at the parsyseda YouTube channel and search for this subject. There is a video going through why you really should be using the newer subclasses. Outlines could be lots of small segments along the same axis which would have lots of implications for export data and mcad data. Design_Outline and cutout must be closed shapes. This is now also used for the 3dx canvas.

RE: Add Collision Detection and ability to XY snap to faces to 3Dx

JM20241029170 — Wed, 08 Jul 2026 18:05:39 GMT

Thanks Steve, got the collision constraints working. Nice that it can be automated, but way harder to maintain and tell exactly where the collision is happening compared to the old tool.

Still having an issue where I can't select a face on the mechanical step model (the red face on the top board) and then XY mate it to a face on the inside of a connector on the main board (the actual brd file that launched the canvas). This used to work in the old tool, I used it to put a 2280 M.2 SSD into a socket that was a component on the main board.

RE: Don't miss our Live, Interactive upcoming OrCAD X Session on July 8th, Wednesday

IshaS — Wed, 08 Jul 2026 15:05:52 GMT

Thank you everyone for the great questions and engagement today. Appreciate your participation!!

Don't miss our Live, Interactive upcoming OrCAD X Session on July 8th, Wednesday

Renu Vibha — Thu, 02 Jul 2026 14:36:25 GMT

Curious about what other users are trying in latest release of OrCAD X—or looking to solve design challenges faster?

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RE: Don't miss our Live, Interactive upcoming OrCAD X Session on July 8th, Wednesday

IshaS — Wed, 08 Jul 2026 15:04:33 GMT

Ok, so for your local workspace, projects are stored in home location.
Open Fole explorer>In address bar type %home%
There you will find folder structure as below

The projects are stored here inside projects folder of workspace.

RE: Don't miss our Live, Interactive upcoming OrCAD X Session on July 8th, Wednesday

LogicNet — Wed, 08 Jul 2026 15:02:30 GMT

Yes this is working.

Are the projects which are visible in my local workspace stored in my local PC?

RE: Don't miss our Live, Interactive upcoming OrCAD X Session on July 8th, Wednesday

TechnoBobby — Wed, 08 Jul 2026 14:58:47 GMT

You can automate the export of variant.lst from Part Manager by setting the AutomationFlag to 1. For additional details, please refer to the second half of the following article and use the script attached there:

Title: How to create Variants.lst file
URL: ask.cadence.com/.../article-viewer

RE: How to Generate Parasitic Reports for All Nets in Allegro PCB Editor, and How Are They Calculated?

Electro Node — Wed, 08 Jul 2026 14:57:33 GMT

Hi FXNTX01,

The above-mentioned report works fine for generating reports for all nets. However, I have not yet tried generating reports by layers. I will test this as well and let you know my findings.

Best Regards,

How to Generate Parasitic Reports for All Nets in Allegro PCB Editor, and How Are They Calculated?

Electro Node — Thu, 16 Apr 2026 15:05:50 GMT

Hi Folks,

Hello I would like to generate parasitic reports (resistance, capacitance, and inductance) for all nets in my Allegro PCB Editor design. Can someone explain the recommended method or workflow to generate these reports from board files?

Additionally, I’m interested in understanding how Allegro calculates these parasitic values. What design parameters (trace geometry, stack‑up, materials, vias, etc.) are considered, and whether the calculations are based on field solvers or rule‑based models.