Allegro X PCB Editor - Recent Threads

RE: mounting IC in 45deg

HS202603175138 — Mon, 31 Aug 2026 06:44:05 GMT

The 45° rotation introduces coordinate rounding when Allegro snaps the pads to its database grid, so a nominal 0.2000 mm gap becomes 0.1999952 mm. The 4.8 nm differences is physically insignificant, but DRC applies a strict comparison. If 0.2 mm is only an internal rule, reduce it slowly or create a footprint-specific exception. If it is the fabricator’s minimum, adjust the pad geometry to provide real manufacturing margin rather than waiving the error.

mounting IC in 45deg

Steik — Mon, 10 Aug 2026 10:46:11 GMT

Hi, I tried to mount a IC in 45 degrees, and that resulted in a landslide of pin to pin spacing DRC.

if I set the ic in 45deg iI get this error:

Constraint Type: NET SPACING CONSTRAINTS

  Constraint value: 0.2 MM

  Actual value:     0.1999 MM

if I measure the Air Gap = 0.1999952 mm

if I set the IC to 90deg I get no errors, and Air gat measures to 0.2mm so a difference in 4,8nm

Can't Orcad do math?

Can this be fixed?

Join us on Wednesday, Sep 9th 2026 for our next LIVE Ask me Anything Session on 'Allegro X PCB Editor Libraries: Creation and Management”

Renu Vibha — Mon, 31 Aug 2026 05:53:57 GMT

Our next session offers a blend of theoretical insights and practical applications, tailored to enhance your understanding of cutting-edge design principles. As always, each session is moderated by Cadence Engineer providing valuable knowledge and actionable techniques.

Do join us here on Wednesday, Sep 9th 2026 for the session at 8:30-9:30PM IST

Topic- 'Allegro X PCB Editor Libraries: Creation and Management”

Bring your questions. Share your experiences. Be part of the conversation

How to install Allegro Free Physical Viewer 16.6？

EL202608245635 — Thu, 27 Aug 2026 16:41:28 GMT

I want to install "Allegro Free Physical Viewer 16.6" to view an old .brd file with old version(16.6), but it is not available on the Cadence website.

Could a moderator please provide me with the download?

RE: How to install Allegro Free Physical Viewer 16.6？

JuanCR — Sun, 30 Aug 2026 20:24:20 GMT

Dbdoctor is not included in the Allegro Free Viewer. You will need a licensed installation in order to access it.

RE: DFF Backdrill to Pad

JuanCR — Fri, 28 Aug 2026 18:44:08 GMT

Hi! Are you intending to configure these values so that it sets up your backdrill? The way to set up the backdrill is actually in Manufacture > NC > Backdrill Setup

DFF Backdrill to Pad

PCB6453 — Wed, 26 Aug 2026 20:01:45 GMT

Hello All,

I'm setting up my DFF constraints for backdrills on vias. The value that I have for Backdrill to antipad is 10 mils. I'm unsure of what value I need to put in for Backdrill to pad if I want the whole pad removed.

Thanks!

RE: How to install Allegro Free Physical Viewer 16.6？

EL202608245635 — Fri, 28 Aug 2026 17:50:29 GMT

Ok, thanks for the reply. Is it possible to use dbDoctor in the newest version of the Allegro free viewer, or is a license of Allegro needed?

RE: How to install Allegro Free Physical Viewer 16.6？

JuanCR — Fri, 28 Aug 2026 17:18:51 GMT

Unfortunately there is no way to provide this installer. You can use a 25.1 installation to uprev the design using dbDoctor.

RE: What is Preventing Designers from Improving Decoupling?

CC202608287943 — Fri, 28 Aug 2026 14:50:00 GMT

Thanks for the detailed explanation. I’m still fairly new to PCB layout, so some of this is new to me, but the point about keeping the trace width closer to the pin width makes sense. I’ll keep the via placement and inductance in mind as well.

What is Preventing Designers from Improving Decoupling?

John T — Mon, 10 Aug 2026 18:16:25 GMT

We see many designs every day but most do not follow the performance recommendations when it comes to power and ground via placement for decoupling capacitors.

Why ?

What is preventing you from pushing your designs to perform at their electrical best:
1. Is it costs?
2. Is it due to manufacturing or fabrication?
3. Is it speed for design completion or DRC management?

The highest level recommendation is to place grounding and power vias inside the capacitor pads

Let’s share some industry experience if anyone has overcome these hurdles or have suggestions or reasons for the approach.

Appreciating any thoughts or comments below.

RE: What is Preventing Designers from Improving Decoupling?

John T — Fri, 28 Aug 2026 12:29:10 GMT

Sometimes it makes you wonder if it would be possible to embed just the ground pad on the lower layer, soldering directly to the inner ground plane...For thin dielectric layers the thickness difference might not be so bad to enable soldering potentially. The technology is already there for making punch openings in the prepreg, or just micro-milling. Hope my meaning is clear.

RE: From Signal Integrity to EMC: Join Daniel Beeker for a Two-Day Science-Based PCB Design Seminar in Derby, United Kingdom in October 2026

Azitech Aps — Fri, 28 Aug 2026 11:18:32 GMT

Thank you, John, for sharing your experience and recommendation. We really appreciate your support and are glad to hear that you found the seminars valuable.

From Signal Integrity to EMC: Join Daniel Beeker for a Two-Day Science-Based PCB Design Seminar in Derby, United Kingdom in October 2026

Azitech Aps — Mon, 20 Jul 2026 15:53:59 GMT

Introduction: PCB Design Has Entered a New Era

Electronic systems continue to evolve at an extraordinary pace. Faster edge rates, higher switching frequencies, compact multilayer stack-ups, dense BGAs, mixed-signal architectures and increasing reliability expectations have fundamentally changed the way printed circuit boards must be designed. In many applications, including aerospace, defence, industrial automation and medical electronics, PCB layout is no longer simply an interconnection exercise; it is a critical part of overall system performance.

Engineers are now expected to achieve first-pass success while meeting demanding signal integrity, EMC and reliability requirements. Every additional prototype, compliance failure or late-stage design modification increases cost and delays product delivery. As a result, organisations are placing greater emphasis on understanding the engineering principles that govern PCB behaviour rather than relying solely on historical design rules.

Many traditional layout practices were developed when switching speeds were considerably slower. Today, however, rise time is often more significant than clock frequency. A design that appears electrically correct in the schematic can still fail because of poor return current paths, discontinuous reference planes, excessive loop area, uncontrolled impedance or inadequate power distribution.

Why Physics Matters More Than Rules of Thumb

Rules and design guidelines remain valuable, but they are most effective when engineers understand why they exist. Science-based PCB design focuses on electromagnetic behaviour rather than memorising isolated layout recommendations. It asks questions such as: Where does the return current flow? How do electric and magnetic fields interact with the PCB structure? What effect will a split reference plane have on a high-speed signal? Why does a seemingly minor layout change create unexpected EMI?

Core Principles of Science-Based PCB Design

Maintain continuous return current paths for every high-speed signal.

Treat reference planes as part of the signal path rather than as passive copper.

Plan PCB stack-ups early to support impedance control and EMC performance.

Reduce loop area to minimise radiated emissions and susceptibility.

Design the power distribution network with low inductance and effective decoupling.

Understand the relationship between placement, routing and electromagnetic field behaviour.

Return Current Paths: Often Overlooked, Always Important

One of the most common causes of EMC and signal integrity problems is an interrupted return current path. High-speed return currents naturally follow the path of least inductance, remaining close to the signal trace on the adjacent reference plane. When that reference is interrupted by plane splits, voids or poorly managed layer transitions, the return current must detour around the discontinuity. The result can be increased loop inductance, higher emissions, greater susceptibility and degraded signal quality.

Signal Integrity, Grounding and Stack-Up Planning

Signal integrity cannot be considered independently from PCB stack-up, grounding strategy and power delivery. Controlled impedance, consistent reference planes and carefully planned layer assignments all contribute to predictable electrical behaviour. Likewise, effective decoupling is not simply about capacitor values; placement, mounting inductance and current loops determine whether transient current demands are met.

From Theory to Practical Engineering

The objective of science-based PCB design is not to make PCB development more theoretical. Quite the opposite. By understanding the underlying physics, engineers can make faster, better-informed design decisions. Rather than following a checklist blindly, they can evaluate trade-offs confidently and identify potential issues before fabrication, reducing PCB re-spins and improving first-pass success.

Daniel Beeker's Engineering Approach

Many engineers know Daniel Beeker through his presentations, design reviews and international technical seminars. With more than 44 years of experience in electronic system design and electromagnetic compatibility, Daniel has developed a teaching style that bridges engineering theory and practical product development. Instead of presenting design rules in isolation, he explains the physical mechanisms behind them, enabling engineers to apply the same reasoning to new technologies and future designs.

His sessions combine real-world PCB examples, practical demonstrations and engineering experience gained from decades of solving challenging EMC and signal integrity problems. This practical approach has made his seminars valuable for PCB designers, hardware engineers, SI engineers, EMC specialists and engineering managers alike.

Benefits for Engineering Teams

Improve first-pass PCB success and reduce costly redesigns.

Strengthen signal integrity and EMC performance.

Understand grounding, return currents and stack-up decisions with greater confidence.

Reduce compliance risk before laboratory testing.

Develop engineering judgement that extends beyond individual design guidelines.

Technical Seminar Hosted by Azitech ApS

To support the engineering community, Azitech ApS, Denmark, will host the Science-Based PCB Design Seminar led by Daniel Beeker on 27–28 October 2026 at Delta Hotels Breadsall Priory Country Club, Derby, England, United Kingdom.

The seminar is intended for experienced PCB designers, hardware engineers, EMC specialists, signal integrity engineers and engineering managers seeking a deeper understanding of the engineering principles that lead to robust, reliable PCB designs. Topics include return current behaviour, grounding, EMI reduction, signal integrity, PCB stack-up planning and practical high-speed design techniques.

An Invitation to the Cadence Community

The Cadence Community has long been a place where engineers share experience, discuss design challenges and exchange practical solutions. We hope this article contributes to that conversation. If the topics discussed here align with the challenges you face in your own designs, we would be delighted to continue the discussion.

As external links may be filtered within the Cadence Community, please feel free to leave a comment or send us a direct message if you would like additional information about the seminar, agenda or registration process. We look forward to engaging with fellow engineers and learning from the wider Cadence community.

Attachment: Seminar Invitation Poster

RE: From Signal Integrity to EMC: Join Daniel Beeker for a Two-Day Science-Based PCB Design Seminar in Derby, United Kingdom in October 2026

Azitech Aps — Fri, 28 Aug 2026 11:11:50 GMT

A quick reminder for the Cadence community: One of the key themes Daniel Beeker will explore is why return-current paths, reference planes and stack-up decisions can have such a significant impact on both signal integrity and EMC performance. Registrations are open at azitech<dot>dk/events.

RE: De assign netname for multiple pins at same time in allegro

Sriranga — Fri, 28 Aug 2026 07:49:31 GMT

Thanks, Vidhya.

Using the Filter option, I was able to generate the .qfnd file. I then edited the QFND file and specified the pins from which I needed to deassign the net name.

Based on the pins listed in the QFND file, I removed the net name only from the particular pins without removing the entire property associated with the net.

I also received a script from my colleague to deassign the net name from the selected pins X & Y location. The script is as follows:

setwindow pcb
ifp
net logic
setwindow form.find
FORM find all_off
FORM find pins YES
setwindow form.mini
FORM mini deassign YES
setwindow pcb
pick 11 12
pick 12 13
pick 13 14
pick 14 15
pick 15 16
pick 16 17
pick 17 18
pick 18 19
pick 19 20
pick 20 21
pick 21 22
pop Done

This approach allows us to deassign the net name from specific pins without affecting the other properties related to the net.

De assign netname for multiple pins at same time in allegro

Sriranga — Sat, 22 Aug 2026 08:14:15 GMT

We can assign the netname to the multiple pins at a same time by using following option( file- import- logic) in PCB editor.

As like that I need to de-assign the multiple pins from different nets.Is there any default option?

For dense board if need to de assign the netname for multiple pins, currently i am deleting entire nets and then I import the netlist...this process give lot of reworks. If anyone have solution for this please give your guidance.

update layout creates a Rectangle "Board Geometry/Top_Room" that cannot be removed

JC202409239850 — Wed, 25 Sep 2024 03:23:32 GMT

This is my first time designing my PCB with Cadence tools. I placed several parts on the PCB design, then I went back to the schematic to make some changes to the connectors. When I came back to the PCB editor and selected "update layout", the editor added all the parts that were not yet placed in a rectangle region named "1". The rectangle cannot be deleted with Edit->Delete command. Can anyone give some hints on how to remove it?

RE: update layout creates a Rectangle "Board Geometry/Top_Room" that cannot be removed

PD20250807594 — Wed, 26 Aug 2026 21:19:30 GMT

Worked for me. After Run Tools > Database check > Check shape outlines, i was able to right click > delete.

RE: How to Change the Color of Embedded Component RefDes in Quick View (Placement Layer) in Allegro X PCB Editor?

Dsharma — Tue, 25 Aug 2026 16:11:29 GMT

Hi,

To change the color of RefDes in Quick Views, navigate to Display > Color/Visibility, and then under Display > Temporary Color, you will be able to change the color.

How to Change the Color of Embedded Component RefDes in Quick View (Placement Layer) in Allegro X PCB Editor?

Electro Node — Fri, 21 Aug 2026 18:28:30 GMT

Hello Everyone,

I am using the Quickviews feature in the Visibility pane of Allegro X PCB Editor to quickly display placement information such as component reference designators, pins, and package boundaries during component placement.
The Placement: TOP and Placement: BOTTOM Quickviews work well for viewing RefDes information without enabling additional subclasses. However, I have noticed that the Reference Designators (RefDes) of Embedded Components appear with a specific default color when displayed through Quickviews.
Is there a way to change the display color of Embedded Component RefDes shown through the Quickviews option?

Regards,

Dileep

RE: De assign netname for multiple pins at same time in allegro

vidhyaparameswari — Mon, 24 Aug 2026 17:44:21 GMT

Hi Sriranga,

You can de-assign pins from their existing nets using the steps outlined below:

Choose Logic → Net Logic from the top menu.
In the Options tab, select the Deassign radio button.
(Optional) Enable Ripup Etch/Conductor if you want the connected traces to be removed automatically.
In the Find filter, ensure Pins is selected.
Click individual pins or drag a window to select multiple pins.
The selected pins will be removed from their current nets and assigned to a dummy net.
Right-click and select Done to complete the operation.

If you later need to assign the pins back to a net, you can follow the same procedure and select the Assign option under Logic → Net Logic, then assign the desired net name to the selected pins.

I hope this helps.

RE: What is Preventing Designers from Improving Decoupling?

avant — Fri, 21 Aug 2026 13:40:13 GMT

Hi John,

I should have clarified - Our designs are usually single-sided with only optional memory and related components on the back side.

Decoupling caps for the top side components are on the top side. Placement is not ideal.

Interesting idea about vias on smd 2 side.

Best Regards

RE: What is Preventing Designers from Improving Decoupling?

John T — Thu, 20 Aug 2026 22:05:51 GMT

Hi Avant, yes this rings a bell with me too having previously designed for high volume production also.

Does anyone ever pre-plan placement to account for smd side1 versus smd side2 assembly? One neat trick we came up with was placing vias in pad for components placed on the smd 2 side. Side 1 being already pasted and soldered; any paste that might come through due to the side 2 soldering will then not cause any interference with production of the opposite side, such as no stencil lifting.

Would be interested to hear any other thoughts or tricks!

RE: What is Preventing Designers from Improving Decoupling?

avant — Thu, 20 Aug 2026 14:50:48 GMT

We don't use via-in-pad.

We produce 1M+ units a year.

Expense and manufacturing issues outweigh benefit for us.

We typically use #2 with vias tied to planes, and wide traces.

We use a lot of 0201 decoupling caps.