Design Entry HDL - Recent Threads

I am not able to generate pdf in allegro dehdl in 24.1 version

Shashank — Thu, 18 Jun 2026 05:42:29 GMT

I have below licenses,

Allegro Library Authoring (PCB Librarian)

Allegro PCB Designer [Schematic]

I am using Allegro PCB Designer [Schematic], and trying to export pdf by going to FILE->PUBLISH PDF

But i am getting below error,

ERROR(SPCOCN-152): The license for this feature could not be
checked out because it is temporarily unavailable. Contact
your administrator to check the license server.

How can i resolve this and generate a pdf.

I am not able to generate pdf in allegro dehdl in 24.1 version

Shashank — Thu, 18 Jun 2026 05:41:47 GMT

I have below licenses,

Allegro Library Authoring (PCB Librarian)

Allegro PCB Designer [Schematic]

I am using Allegro PCB Designer [Schematic], and trying to export pdf by going to FILE->PUBLISH PDF

But i am getting below error,

ERROR(SPCOCN-152): The license for this feature could not be
checked out because it is temporarily unavailable. Contact
your administrator to check the license server.

How can i resolve this and generate a pdf.

Newly created blocks in Allegro 24.1 cannot be saved

HW202602055335 — Thu, 05 Feb 2026 10:18:25 GMT

Recently I am trying to use hierarchical design approaches to capture ETS800 schematic in Allegro 24.1. But when we created a new block and clicked save, there is an error message popping up like below:

Error in netlisting:Error reading xxxxx_lib/block1/entity/verlog.v no such view

Is there a allegro design entry hdl free viewer?

NS202407245333 — Thu, 27 Nov 2025 13:40:00 GMT

I want to open a design in read-only offline mode.

Cadence Tech Day Invitation- Allegro X System Capture Deep Dive (Aug 19–20, Bengaluru)

Renu Vibha — Thu, 14 Aug 2025 10:56:25 GMT

Join us for an exclusive full-day technical event at the Cadence Bengaluru office on August 19th or 20th, focused on the cutting-edge capabilities of Cadence Allegro X System Capture — our next-gen schematic design platform.

Led by our Product Engineering experts, this session offers hands-on insights into advanced features and workflows that boost design accuracy and productivity.

Choose your preferred date (same content on both days)
Kindly confirm attendance and share participant details with Shikhar Dwivedi (dshikhar@cadence.com) or Bhargava Hegde (hbhargav@cadence.com)

Let’s walk the future of design together!

Console command _PAGEInsert with key "noconfirm"

Igor S — Tue, 01 Jul 2025 11:21:01 GMT

HI,

I use console command "_PAGEInsert -noconfirm" in order to insert new page from SKILL script.

And I dint want any user confirmation, so I use "noconfirm" key.

But, upon insertion, it pops up the completion message with OK button, and stuck till pressing it or ENTER. So, despite "noconfirm" key - the iteraction with user still needed.

How can I suppress this user input request?

Thanks

Run SKILL file from DE HDL console

Igor S — Wed, 28 May 2025 09:22:08 GMT

HI,

Is it possible to launch the SKILL file that I have (with .il extension) directly by DEHDL console command?

Thanks

DE HDL to SKILL connection problem

Igor S — Mon, 26 May 2025 06:22:36 GMT

Hi,

I use Allegro Design Entry HDL 23.1.

With project opened and DE HDL running, in console window I enter "cnskill -i -nongraph"

Then, SKILL window opens with ">" sign.

Entering "cnmpsIsExported()", I get "t" - i.e. session is ready to be imported, right?

But, when i enter "handle=cnmpsImport()", it outputs message about timeout expired while contacting server.

What may be wrong?

Thanks

Assign Xnet pins in HDL design

EO202501307419 — Mon, 14 Apr 2025 13:13:14 GMT

Hello,

I have a problem defining my Xnets. I already defined my Xnets in PCB alegro, layout . Since layout only creates Xnets for the pins that has Xnet property, I need to define Xnet pins in my HDL entry design, schematic as well. However, There is no ^ edit part^ in HDL entry when I right click on it, so I can add class, or define pins. Where can i set this?

Design Entry HDL error spcocd-152

VC202503176623 — Tue, 18 Mar 2025 00:40:59 GMT

Hi,

I got a error about the "error (spcocd-152): Port SWDIO in cell 'adapter_jlink' is missing in block

Please advise what's the message mean for, and how to resolve this problem, thanks

Some net names are missing in netlist file generated in DEHDL

ronniezh — Thu, 02 Jan 2025 07:39:34 GMT

Hi Experts,

When I generated Netlist file in DEHDL(Menu Tools -> Packager Utilities -> Netlist Reports) and choose Concise Netlist mode like below:

I found there are some net names missing in my Netlist report:. E.g., VCC and PBKG signal names in below schematic don't exist in the Netlist report.

Only The test points TP_VCC_S1 and TP_PBKG_S1 appear.

Most the signal names with the similar structure exist in the Netlist report correctly. Is there something wrong with my signal names or method to generate Netlist report?

Any input would be appreciated! Thanks!

Best regards, Ronnie

Issue with Signal naming in design entry HDL

SIVAREDDY TI — Thu, 26 Dec 2024 06:15:57 GMT

Hi,

I am working on a hierarchical design ,in the subblock i am trying to name the signals names of the Devicefrom place signal name -->entering all the names

but it should be coming serially in the actual schematic page but they are not appearing to name the nets.

How to import the Design Entry DHL schematic Design to OrCAD Capture Schematic

RohitRohan — Tue, 24 Dec 2024 14:52:20 GMT

Dear Community,

I have a schematic design created in Design Entry HDL, and the file is saved with the .cpm extension. I am currently looking to import this schematic design into OrCAD Capture.

If anyone has a document or video tutorial outlining the detailed steps or procedures for importing a Design Entry HDL schematic design (.cpm) into OrCAD Capture, I would greatly appreciate it if you could share it with me.

Thank you in advance for your assistance and support.

Best regards,
Rohit Rohan

How to modify SIG_NAME and LOCATION in backend text file

ronniezh — Mon, 16 Dec 2024 06:20:16 GMT

Hi Experts,

I want to modify the SIG_NAME and LOCATION properties in backend project text file, rather than in Design Entry HDL, which enable feasibility of automatic schematic modification by scripting.

For example, in below screen capture I want to modify item in specific page 25:

SIG_NAME properties: "APU12_60F", "APU12_60S" in orange color;
LOCATION properties: "C1_S1", "K1_S1"

I find there are several text files in project directory: .../project_name/worklib/project_name/sch_1/

The SIG_NAME properties: "APU12_60F", "APU12_60S" and the LOCATION properties: "C1_S1", "K1_S1" can be found in page25.csv and page25.csa. But the schematic didn't update after I modify the SIG_NAME and LOCATION in page25.csv and page25.csa file. I try to restart Design Entry HDL and Allegro EDM Flow Manager, but the schematic still didn't update as I expected.

Any inputs are appreciated!

Thanks in advance!

Best regards,

Ronnie

How to combine multiple schematic and PCB layouts to a single project

RohitRohan — Thu, 22 Aug 2024 07:11:14 GMT

Hai Community,

I have a project where it consists of multiple schematic designs and multiple PCB layouts. These schematic design and PCB are combination for a single system but having different schematic files and different PCB files.

Instead of having multiple schematic designs and multiple PCBs, I want combine them. Is it possible in Design Entry HDL or is there any other products under Cadence for this requirement.

Regards,

Rohit Rohan

How to copy the design entry HDL file from one PC to another PC and open the design in 2nd PC.

RohitRohan — Wed, 21 Aug 2024 11:28:02 GMT

Dear Community,

I have received a schematic design from one of our clients, they have designed the schematic design using design entry HDL and they have sent the design files which includes the CPM file.

When I tried to open the CPM file in my PC I am getting the following error. (The errors are in sequence)

ERROR(SPCOCN-175): The env variable could not be expanded because of the illegal ppt path: $PCBDW_LIB/reflib/model_sym/part_table_mech.ptfEnvironment variable PCBDW_LIB not set.. Ensure that you provide
the correct value of the ppt value.

WARNING(SPCOCN-515): Design Name: <721992929_lib>12323924A.SCH.1.1
All the required libraries are not included in the cds.lib file. Make sure your project setup has all the necessary libraries. Exit Design Entry HDL and add the required libraries to the project using the Project Setup utility of Project Manager. The parts missing from the available libraries are:
CHARGER.SYM.1.1
SOC102.SYM.1.1

ERROR(SPCOCN-1334): Library changer_module not found in cds.lib list.

WARNING(SPCOCN-674): Error(s) in D:\charger\SOC
WARNING(SPCOCN-675): Invalid environment variable: on line 2.

Can anyone help me resolve this error.

Regards,

Rohit Rohan

Not add suffix to a subdesign

AB_1720516286397 — Tue, 09 Jul 2024 09:18:51 GMT

Hi all,

I have two sub-designs.
I have added SUBDESIGN_SUFFIX property for one of them manually.
I only instantiated once the other one and I don't want to add suffix to this one.
Is there any way to do that.

Really appreciate your quick answers.
Thank you in advance.

Plotting to PDF in Design Entry HDL

dd2661 — Mon, 10 Jun 2024 18:56:34 GMT

I am having issues plotting a Design Entry HDL 17.4 schematic to a PDF. When I go to plot, there is missing text and graphics along the bottom and right hand margins, much like this post from 2010: https://community.cadence.com/cadence_technology_forums/pcb-design/f/pcb-design/16587/problem-of-plotting-a-schematic-in-design-entry-hdl. Adjusting the layout, page size, and percentage fit does nothing.

It seems that this bug has not been fixed, and the publish PDF feature recommended in the previous post is unavailable in my license pack. Does anyone have a solution for printing a PDF of a schematic while retaining all text and graphics on a single page? I have rifled through every imaginable option in the plot settings and no luck. This is a very basic function of any schematic entry tool, and I'm absolutely amazed that this bug has not been addressed in 14 years...

Any suggestions would be greatly appreciated.

Changing attributes using console command or script?

Console501 — Wed, 05 Jun 2024 09:37:47 GMT

Hi,

Can anybody please help me develop a script for changing the values of "attributes" of a certain component.

say i want to make the $LOCATION or the Tolerance of a certain Capacitor upon user click or selection.

Any help, even if just console commands will be much appreciated.

Thanks,

Change the name of a group of similar nets

AGard — Mon, 03 Jun 2024 17:12:00 GMT

Hello,

At a high level, I want to change all nets within a multi-page schematic with a certain substring to another while maintaining the rest of the string. Example: 2 signals on 2 pages are: "this_signal_name_1" "this_is_another_signal." I want to change "this" to "diff_string" and have the 2 signals on different pages updated to "diff_string_signal_name" and "diff_string_is_another_signal." All prefixes and suffixes of the substring should be maintained.

To clarify the question, I have a multi-page schematic in Allegro Design Entry HDL. There is a signal name applied across the pages that I wish to change with one set of commands, e.g. using a Global Property Change. Here is the problem. The nets all have the same prefix, but have different naming conventions given their location and connection within the schematic. Example "I2C_TX_Temp_Sense," I2C_TX_DIMM_1," "I2C_RX_MUX_3" all need to have "I2C" changed to "I3C." Do not adhere to this example rigidly, this is just the general concept. The problem I have with the Global Property Change is that I can find all nets with the "I2C" prefix when I use "I2C*." When I try to change it to "I3C*" in the Value category, it will change all nets across the design to "I3C*" instead of saving the suffix. I know there are ways to go page by page and change the net names as a group using the "find SIG_NAME=I2C*" command then changing the test file with CTRL+E, but this seems inefficient.

I have so far been unable to get the "find globalFind {[Entire Design]}..." or "find -scope "Entire Design" ..." commands to work. I cannot find proper documentation in the Cadence Help portal for what I am looking for. I would think this is the correct idea given that I can accomplish this task on individual pages with the "find SIG_NAME=I2C*" command.

Thanks,

AGard

Add Prefix into the current schematic

Son — Thu, 23 May 2024 20:52:09 GMT

I know to add a prefix to the schematic but I don't know how to add a prefix to the current schematic and keep the same ref. des.

For example, my current schematic ref des like; U1, C1, and R1.

I want to add a prefix "09" into the ref des after "U". New schematic ref des are U091, C091, and R091.

Can you please help?

Thanks,

Son Nguyen

How to assign signal name to specific PATH automatically

ronniezh — Mon, 01 Apr 2024 06:10:34 GMT

Hi All,

I need to assign many signal names to corresponding PATH and LOCATION. The mapping relationship between signal name and PATH are specified in a table.

As shown in below picture, the PR? is an identical component which is in multi-symbol version format. I can use copy/paste, multi-section to generate below circuits.

This is what I want to do. Assign different signal name to each of these independent components.

But the PATH(pin number in daughter card) and net name connections are specified in a table. Since the count of block abovementioned I need to create and assign is too many, it will be easy to have error if I have to do it manually and take too long time.

I tried to create group and open the PATH/signal name in text change editor, but it doesn't work even I add signal name in it.

Does anyone know if there is any way to do this automatically?

Graphics Tab Disappear in Part Information Manager

ronniezh — Fri, 15 Mar 2024 06:50:28 GMT

Hi All,

For unknown reasons, the graphics tab in my Part Information Manager of DesignEntry HDL disappeared. I couldn't enable it from other settings after I tried to explore other settings I could try.

The version I'm using is Allegro 17.4. This graphic tab works normally before, it just disappear in recent days. I tried to restart my software and it still cannot pop up.

Does any one have this issue before?

Highly appreciated if any suggestion!

Abundant Concepthdl.exe folders under my project folder

ronniezh — Fri, 15 Mar 2024 06:39:28 GMT

Hi all,

I'm using Allegro 17.4 DesignEntry HDL to capture schematic. There are many abundant folder naming 'Concepthdl.exe[xxx]' under my project folder. As shown below, this folder has two files, 'crashdump.dmp' and 'errorlog.xml'. Does any know what these folders are and can I just delete them?

Many thanks in advance!

How to create a compressed BOM in Allegro schematic in Design Entry

heidi099 — Mon, 29 Jan 2024 01:10:27 GMT

I am using the Allegro Design Authoring : Design Entry HDL and I have a compiled and annotated schematic.

I want to create BOM.

Part1, 3, R1, R2, R3

Part2 , 4, C1, C2, C3, C4

Part3 , 1 C10, C11

etc

How do I set up the template to create such an output.