Design Entry HDL - Recent Threads

RE: Plotting to PDF in Design Entry HDL

Andrew Beckett — Wed, 24 Jun 2026 09:16:07 GMT

Jean-Charles,

Not really the best way to communicate (likely I got this post, but I don't follow this forum since I'm a Custom IC guy), but from what I can see the post you are referring to has been deleted (I can't find it anywhere). I will ask my IT colleagues if they can find out why - they can probably determine who deleted it (likely the original author or another moderator).

Andrew

Plotting to PDF in Design Entry HDL

dd2661 — Mon, 10 Jun 2024 18:56:34 GMT

I am having issues plotting a Design Entry HDL 17.4 schematic to a PDF. When I go to plot, there is missing text and graphics along the bottom and right hand margins, much like this post from 2010: https://community.cadence.com/cadence_technology_forums/pcb-design/f/pcb-design/16587/problem-of-plotting-a-schematic-in-design-entry-hdl. Adjusting the layout, page size, and percentage fit does nothing.

It seems that this bug has not been fixed, and the publish PDF feature recommended in the previous post is unavailable in my license pack. Does anyone have a solution for printing a PDF of a schematic while retaining all text and graphics on a single page? I have rifled through every imaginable option in the plot settings and no luck. This is a very basic function of any schematic entry tool, and I'm absolutely amazed that this bug has not been addressed in 14 years...

Any suggestions would be greatly appreciated.

RE: Plotting to PDF in Design Entry HDL

JCTEYSSIER0 — Wed, 24 Jun 2026 06:53:34 GMT

Sorry to "poluate" this thread but this is a way i found to contact you

Seems the automatic anti abuse is a really too much agressive, even if the content is approved by you.

You already approve my "how-to-avoid-such-same-shape-spacing-problem" on june 18; june 20 i receive a email to inform me my post was reflag as abuse, june 22 i receive a email "its ok, rewieved and now onlin"; june 22 (same day) re flaged asa abuse, june 22 (one minute later!) "ok, now it is re re reviewed" and now online; tthis morning i can not see anymore my post Slight smile
Note: while writting this message i receive an other email saying: its ok now

But... stil no post available

RE: Plotting to PDF in Design Entry HDL

JCTEYSSIER0 — Wed, 24 Jun 2026 06:49:52 GMT

Hello Andew,

Sorry to "poluate" this thread but this is a way i found to contact you

Seems the automatic anti abuse is a little too much agressive, even if the content is approved by you.

You already approve my "how-to-avoid-such-same-shape-spacing-problem" on june 18; june 20 i receive a email to inform me my post was reflag as abuse, june 22 i receive a email "its ok, rewieved and now onlin"; june 22 (same day) re flaged asa abuse, june 22 (one minute later!) "ok, now it is re re reviewed" and now online; tthis morning i can not see anymore my post 🙂

the url was (broken now)

https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66086/how-to-avoid-such-same-shape-spacing-problem

Figth against the automatic anti spam....

Regards,

Jean-Charles

RE: Newly created blocks in Allegro 24.1 cannot be saved

rg13 — Thu, 18 Jun 2026 08:58:31 GMT

In oreder to generate a VHDL file for a part, please use the following command line.

newgenasym -i <path to library>/<block name> -n <block name> -t <temp dir>

Newly created blocks in Allegro 24.1 cannot be saved

HW202602055335 — Thu, 05 Feb 2026 10:18:25 GMT

Recently I am trying to use hierarchical design approaches to capture ETS800 schematic in Allegro 24.1. But when we created a new block and clicked save, there is an error message popping up like below:

Error in netlisting:Error reading xxxxx_lib/block1/entity/verlog.v no such view

I am not able to generate pdf in allegro dehdl in 24.1 version

Shashank — Thu, 18 Jun 2026 05:41:47 GMT

I have below licenses,

Allegro Library Authoring (PCB Librarian)

Allegro PCB Designer [Schematic]

I am using Allegro PCB Designer [Schematic], and trying to export pdf by going to FILE->PUBLISH PDF

But i am getting below error,

ERROR(SPCOCN-152): The license for this feature could not be
checked out because it is temporarily unavailable. Contact
your administrator to check the license server.

How can i resolve this and generate a pdf.

RE: I am not able to generate pdf in allegro dehdl in 24.1 version

Shashank — Thu, 18 Jun 2026 07:19:53 GMT

Thank for the reply rg13

RE: I am not able to generate pdf in allegro dehdl in 24.1 version

rg13 — Thu, 18 Jun 2026 07:10:59 GMT

Hi Shashank,

To use this feature, Allegro_Design_Publisher is needed.

For more details, refer following link:

Article (20492928) Title: Getting ERROR (SPCOCN-152) when trying to use Publish PDF option
URL: https://ask.cadence.com/ASK/article-viewer?id=a1O3w00000A44OhEAJ&pageName=article-viewer

RE: I am not able to generate pdf in allegro dehdl in 24.1 version

rg13 — Thu, 18 Jun 2026 07:10:50 GMT

Hi Shashank,

To use this feature, Allegro_Design_Publisher is needed.

For more details, refer following link:

Article (20492928) Title: Getting ERROR (SPCOCN-152) when trying to use Publish PDF option
URL: https://ask.cadence.com/ASK/article-viewer?id=a1O3w00000A44OhEAJ&pageName=article-viewer

I am not able to generate pdf in allegro dehdl in 24.1 version

Shashank — Thu, 18 Jun 2026 05:42:29 GMT

I have below licenses,

Allegro Library Authoring (PCB Librarian)

Allegro PCB Designer [Schematic]

I am using Allegro PCB Designer [Schematic], and trying to export pdf by going to FILE->PUBLISH PDF

But i am getting below error,

ERROR(SPCOCN-152): The license for this feature could not be
checked out because it is temporarily unavailable. Contact
your administrator to check the license server.

How can i resolve this and generate a pdf.

RE: Newly created blocks in Allegro 24.1 cannot be saved

SZ202605217846 — Fri, 22 May 2026 02:52:04 GMT

hello, could i know how you solve this issue? because i meet the same issue as you and have no way to deal with it.

RE: Newly created blocks in Allegro 24.1 cannot be saved

SZ202605217846 — Fri, 22 May 2026 02:45:06 GMT

hello, could i know how you solve this issue as i meet the same issue as you? and have no way to solve it.

RE: Newly created blocks in Allegro 24.1 cannot be saved

rg13 — Mon, 09 Feb 2026 09:43:29 GMT

I have already contacted you via separate channel of communication and working with you to debug this issue.

RE: Is there a allegro design entry hdl free viewer?

Akshay khosla — Thu, 27 Nov 2025 15:41:39 GMT

There is no HDL free viewer available however an enhancement CCR has already been filed for this.

Is there a allegro design entry hdl free viewer?

NS202407245333 — Thu, 27 Nov 2025 13:40:00 GMT

I want to open a design in read-only offline mode.

Cadence Tech Day Invitation- Allegro X System Capture Deep Dive (Aug 19–20, Bengaluru)

Renu Vibha — Thu, 14 Aug 2025 10:56:25 GMT

Join us for an exclusive full-day technical event at the Cadence Bengaluru office on August 19th or 20th, focused on the cutting-edge capabilities of Cadence Allegro X System Capture — our next-gen schematic design platform.

Led by our Product Engineering experts, this session offers hands-on insights into advanced features and workflows that boost design accuracy and productivity.

Choose your preferred date (same content on both days)
Kindly confirm attendance and share participant details with Shikhar Dwivedi (dshikhar@cadence.com) or Bhargava Hegde (hbhargav@cadence.com)

Let’s walk the future of design together!

RE: Cadence Tech Day Invitation- Allegro X System Capture Deep Dive (Aug 19–20, Bengaluru)

Zhifeng Jin — Thu, 14 Aug 2025 13:13:38 GMT

It is good to know about important information and thanks for sharing !

RE: Cadence Tech Day Invitation- Allegro X System Capture Deep Dive (Aug 19–20, Bengaluru)

TechiEE12 — Thu, 14 Aug 2025 12:57:45 GMT

Yes DE-HDL is approaching end of life shortly.You may refer to the details avaliable on ask.cadence.com. For your quick access you can refer to the below article

Official End of Life (EOL) Notification – Allegro Design Entry HDL

RE: Cadence Tech Day Invitation- Allegro X System Capture Deep Dive (Aug 19–20, Bengaluru)

Zhifeng Jin — Thu, 14 Aug 2025 11:22:55 GMT

Recently, I have been learning how to use DE-HDL. One time, I received a push article from the official website(Moving DE-HDL PCB Projects to Allegro X System Capture - System, PCB, & Package Design - Cadence Blogs - Cadence Community),

which mentioned that DE-HDL has started planning to discontinue and DE-HDL executors will be phased out.

Is this true?

RE: Console command _PAGEInsert with key "noconfirm"

Igor S — Wed, 09 Jul 2025 06:51:51 GMT

It does not work as you describe.

After page insertion, it issues completion message and waiting for pressing OK

Console command _PAGEInsert with key "noconfirm"

Igor S — Tue, 01 Jul 2025 11:21:01 GMT

HI,

I use console command "_PAGEInsert -noconfirm" in order to insert new page from SKILL script.

And I dint want any user confirmation, so I use "noconfirm" key.

But, upon insertion, it pops up the completion message with OK button, and stuck till pressing it or ENTER. So, despite "noconfirm" key - the iteraction with user still needed.

How can I suppress this user input request?

Thanks

RE: Console command _PAGEInsert with key "noconfirm"

rg13 — Wed, 09 Jul 2025 06:39:26 GMT

I tried with following command in DEHDL's console window:

_PAGEInsert 1 2 -nosave -noconfirm

It works without any issue and does not ask for any confirmation and no pop up comes-up on display.

Screenshot from manual:



For your reference here is the link of manual for your from ASK portal:
Allegro Design Entry HDL Reference Guide -- Console Command Reference

RE: Run SKILL file from DE HDL console

Elecguy — Fri, 30 May 2025 12:17:23 GMT

I am almost 100% sure that you can ... I've seen somewhere out there that there is SKILL for DE-HDL, but I think it's not as direct as in Allegro where you can just run code directly from the command line.

Run SKILL file from DE HDL console

Igor S — Wed, 28 May 2025 09:22:08 GMT

HI,

Is it possible to launch the SKILL file that I have (with .il extension) directly by DEHDL console command?

Thanks