<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.cadence.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>PSpice - Recent Threads</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice</link><description /><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>Exporting PSPICE netlist with Subckt parameters</title><link>https://community.cadence.com/thread/66043?ContentTypeID=0</link><pubDate>Wed, 03 Jun 2026 20:44:16 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:da0c4f7d-df11-439b-bfd0-381a4a309f62</guid><dc:creator>SC202412036016</dc:creator><slash:comments>4</slash:comments><comments>https://community.cadence.com/thread/66043?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/66043/exporting-pspice-netlist-with-subckt-parameters/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I am trying to export a PSPICE netlist of a simple subcircuit where I have to pass in parameters, however parameter definition is happening after ENDS, instead of the top line where the subcircuit is being defined. There is a .PARAMS in the subckt line however the actual parameter (lval) is showing up right at the end. Any ideas on where the issues may be?&lt;/p&gt;
&lt;p&gt;I cannot seem to attach a screenshot of the template settings, but if this works for anyone would be great if you can send a screenshot of the template settings where the ParamList is displayed at the top.&lt;/p&gt;
&lt;p&gt;1. To extract the netlist I go to Tools &amp;gt; Create Netlist&lt;/p&gt;
&lt;p&gt;2. Here is the output:&amp;nbsp;&lt;/p&gt;
&lt;p&gt;* source BLOCK_AOL&lt;br /&gt;.SUBCKT Aol_Block InN InP OutN OutP PARAMS : &lt;br /&gt;G_G1 OUTP OUTN INP INN -1u&lt;br /&gt;L_L1 N00976 OUTN {LVAL} TC=0,0 &lt;br /&gt;R_R2 N00976 OUTP 1M TC=0,0 &lt;br /&gt;.ENDS Aol_Block&lt;br /&gt;.PARAM lval=1n&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Persistent netlisting error</title><link>https://community.cadence.com/thread/66023?ContentTypeID=0</link><pubDate>Mon, 01 Jun 2026 12:07:33 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9ebdcf5b-d725-4fbc-96f4-680f699d1bd0</guid><dc:creator>AG202606016357</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66023?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/66023/persistent-netlisting-error/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello,&lt;/p&gt;
&lt;p&gt;I&amp;#39;m using &amp;quot;PSpice for TI&amp;quot; to simulate a DCDC converter implementing a specific TI PWM controller (hence the selection of the simulation tool).&lt;/p&gt;
&lt;p&gt;My schematic is drawn and seems correct. Still, when I launch the netlist generation, I get the following error message:&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&amp;quot;ERROR(ORCAP-15065): There are netlisting errors.&lt;/p&gt;
&lt;p&gt;Check the session log.&amp;quot;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;In the session log, I find:&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&amp;quot;INFO(ORNET-1041): Writing PSpice Flat Netlist \\xxx\yyy\SCHEMATIC1\SCHEMATIC1.net&lt;br /&gt;INFO(ORNET-1169): Unable to open the property mapping file: devparam.txt. To resolve this problem, ensure that PSpice.ini exists at the correct location. After that check Library Path in simulation settings contains &amp;lt;installation-path&amp;gt;/tools/pspice/library path and then create the netlist again.&lt;br /&gt;INFO(ORNET-1162): Unable to create design property file&amp;quot;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;I completed the proposed checks and everything is OK.&lt;/p&gt;
&lt;p&gt;I gave a try with a very simple schematic (1 DC source, 1 ideal R and 1 ideal C). I got the exact same error.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;How can I solve this error?&lt;/p&gt;
&lt;p&gt;What should I do?&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Thanks for helping me.&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>PSpice Special Component: Watch1</title><link>https://community.cadence.com/thread/66018?ContentTypeID=0</link><pubDate>Sun, 31 May 2026 19:15:05 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6e5e6cbd-03ce-4c24-b6f3-c311b62bb7ee</guid><dc:creator>AyushD</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66018?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/66018/pspice-special-component-watch1/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;.WATCH command&amp;nbsp;enables user&amp;nbsp;to observe voltage at node in simulation status windows while simulation is in progress.&lt;/p&gt;
&lt;p&gt;Attach this part (WATCH1) at node or net which you will like to observe during the simulation. After this, you need to define following three parameters on symbol instance:&lt;br /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Analysis:&lt;/strong&gt; Assign the one of the following three values depending upon the type of analysis being performed:&lt;br /&gt;&amp;nbsp; &amp;nbsp;DC&lt;br /&gt;&amp;nbsp; &amp;nbsp;AC&lt;br /&gt;&amp;nbsp; &amp;nbsp;TRAN&lt;br /&gt;&lt;br /&gt;&lt;strong&gt;HI:&lt;/strong&gt; Assign a numeric value to define upper limit of voltage&lt;br /&gt;&lt;strong&gt;LO:&lt;/strong&gt; Assign a numeric value to define lower limit of voltage&lt;br /&gt;&lt;br /&gt;Simulator pauses if voltage at node is outside of range defined by HI and LO.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Unable to Upload Images</title><link>https://community.cadence.com/thread/65987?ContentTypeID=0</link><pubDate>Mon, 04 May 2026 16:26:34 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ad134f72-e1c3-4879-a10b-27ff4f59ac6e</guid><dc:creator>MrTF</dc:creator><slash:comments>3</slash:comments><comments>https://community.cadence.com/thread/65987?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65987/unable-to-upload-images/rss?ContentTypeId=0</wfw:commentRss><description>&lt;div&gt;
&lt;p&gt;Dear all,&lt;/p&gt;
&lt;p&gt;I have tried several times to upload an image from my simulation in order to post a question.&lt;/p&gt;
&lt;p&gt;Unfortunately, this has not been possible so far. Each time, I receive a message advising me to contact the administrator.&lt;/p&gt;
&lt;p&gt;Could you please let me know how to proceed or whom I should contact to resolve this issue?&lt;/p&gt;
&lt;p&gt;Thank you in advance for your support.&lt;/p&gt;
&lt;/div&gt;
&lt;p&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Model stepping in PSpice</title><link>https://community.cadence.com/thread/65974?ContentTypeID=0</link><pubDate>Thu, 30 Apr 2026 16:38:48 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ef6a8434-52ad-47e6-99cf-fca5a77caf59</guid><dc:creator>IshaS</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/65974?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65974/model-stepping-in-pspice/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Starting with &lt;strong&gt;SPB 25.1&lt;/strong&gt;, PSpice introduces &lt;strong&gt;model stepping&lt;/strong&gt;, which allows multiple models of the same component to be simulated in a single run and compared directly in the Probe window. All results are stored in one data file, making side‑by‑side analysis simple and efficient.&lt;/p&gt;
&lt;p&gt;This is done using the. modelstep directive. For example, as shown in the following image, for the given circuit, a&amp;nbsp;.modelstep&amp;nbsp;statement has been defined as:&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;@PSpice:&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;.modelstep STPSC10065D MUR1560&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;Now, tool will simulate the design with both the PSpice models for D1 as defined in the above statement (STPSC10065D and MUR1560).&lt;/p&gt;
&lt;p&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/110/pastedimage1777567099543v1.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;When the simulation is run, PSpice automatically steps through both models and displays their results together in the Probe window. This makes it easy to compare waveforms and performance and select the most suitable device. The Probe output also shows the total job time for all stepped models.&lt;/p&gt;
&lt;p&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/110/pastedimage1777567114066v2.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;Try this and share your insights!&lt;/p&gt;
&lt;p&gt;&lt;br /&gt; Happy Learning !!&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Efficient Method to Perform Temperature Sensitivity Analysis and Rank Dominant Components in PSpice</title><link>https://community.cadence.com/thread/65973?ContentTypeID=0</link><pubDate>Thu, 30 Apr 2026 15:43:57 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7a1fad12-2cbe-495b-81fd-c23653c359b5</guid><dc:creator>MrTF</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/65973?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65973/efficient-method-to-perform-temperature-sensitivity-analysis-and-rank-dominant-components-in-pspice/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p data-start="151" data-end="361"&gt;I am working on a precision analog circuit and I want to assess &lt;strong data-start="215" data-end="242"&gt;temperature sensitivity&lt;/strong&gt; and identify which components dominate performance variation due to temperature in an &lt;strong data-start="329" data-end="360"&gt;efficient and automated way.&lt;/strong&gt;&lt;/p&gt;
&lt;p data-start="363" data-end="445"&gt;My objective is not simply to observe output variation of a specific performance metric versus temperature, but to:&lt;/p&gt;
&lt;ul data-start="447" data-end="764"&gt;
&lt;li data-start="447" data-end="571"&gt;Quantify the sensitivity of a performance metric (e.g., output current, impedance, or noise) with respect to temperature&lt;/li&gt;
&lt;li data-start="572" data-end="671"&gt;Attribute this variation to individual components (R, L, C, coupling factors, parasitics, etc.)&lt;/li&gt;
&lt;li data-start="672" data-end="764"&gt;Rank components based on their contribution to the overall temperature-induced variation&lt;/li&gt;
&lt;/ul&gt;
&lt;p data-start="766" data-end="1105"&gt;One approach I considered is to encode temperature effects as equivalent tolerances (i.e., mapping TC-induced drift into % variation) and then perform a standard sensitivity or worst-case analysis. However, this would require maintaining two versions of the circuit (nominal vs &amp;ldquo;temperature-perturbed&amp;rdquo;), which is not practical or scalable.&lt;/p&gt;
&lt;p data-start="1107" data-end="1323"&gt;To clarify, I am &lt;strong data-start="1124" data-end="1178"&gt;not referring to a simple global temperature sweep&lt;/strong&gt; or single-parameter variation. I am looking for a method that enables &lt;strong data-start="1249" data-end="1322"&gt;systematic decomposition of temperature effects across all components&lt;/strong&gt;.&lt;/p&gt;
&lt;p data-start="1325" data-end="1392"&gt;&amp;nbsp;Is there a rigorous and efficient workflow in PSpice/Cadence to:&lt;/p&gt;
&lt;ul data-start="1393" data-end="1570"&gt;
&lt;li data-start="1393" data-end="1509"&gt;perform sensitivity analysis with respect to temperature and&lt;/li&gt;
&lt;li data-start="1510" data-end="1570"&gt;automatically identify and rank the dominant contributors?&lt;/li&gt;
&lt;/ul&gt;
&lt;p data-start="1572" data-end="1713"&gt;Any guidance on built-in features I may miss would be highly appreciated.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>OP467 Component - Simulation Model Issue</title><link>https://community.cadence.com/thread/65919?ContentTypeID=0</link><pubDate>Tue, 14 Apr 2026 11:07:43 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:dc6c7e76-ec91-412e-8d78-38de4ceae446</guid><dc:creator>MrTF</dc:creator><slash:comments>2</slash:comments><comments>https://community.cadence.com/thread/65919?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65919/op467-component---simulation-model-issue/rss?ContentTypeId=0</wfw:commentRss><description>&lt;div&gt;
&lt;p&gt;Dear all,&lt;/p&gt;
&lt;p&gt;I am using the &lt;strong&gt;OP467&lt;/strong&gt; model, which I selected via (Menu)&lt;br /&gt; &lt;strong&gt;Place &amp;rarr; Component &amp;rarr; PSpice Category Model&lt;/strong&gt;.&lt;/p&gt;
&lt;p&gt;During simulation, I receive the following warning:&lt;/p&gt;
&lt;blockquote&gt;
&lt;p&gt;&lt;strong&gt;DRC Type:&lt;/strong&gt; Electrical&lt;br /&gt; &lt;strong&gt;Warning (ORCAP‑2445)&lt;/strong&gt;&lt;br /&gt; Instance &lt;strong&gt;UxD&lt;/strong&gt;, &lt;strong&gt;SCHEMATIC1&lt;/strong&gt;, &lt;strong&gt;PAGE 1&lt;/strong&gt; (XXX.xx, XXX.xx),&lt;br /&gt; not found in the configured libraries.&lt;/p&gt;
&lt;/blockquote&gt;
&lt;p&gt;Could someone please clarify:&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;What exactly does this warning refer to?&lt;/li&gt;
&lt;li&gt;Does it imply any potential malfunction or inaccuracy in the simulation results?&lt;/li&gt;
&lt;li&gt;Why is the component reported as &amp;ldquo;not found in the configured libraries,&amp;rdquo; even though it appears to be located under the &lt;strong&gt;CIS Unified Library&lt;/strong&gt;?&lt;/li&gt;
&lt;li&gt;In the model I use there is a parameter with the description &amp;quot;LEVEL 3&amp;quot;. To what this parameter refers to?&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;Any guidance would be greatly appreciated.&lt;/p&gt;
&lt;p&gt;Thank you in advance.&lt;/p&gt;
&lt;/div&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Ground connection in simulating three phase PFC</title><link>https://community.cadence.com/thread/65896?ContentTypeID=0</link><pubDate>Fri, 03 Apr 2026 09:50:19 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:bbb77d77-0c4c-4420-90c9-61cf43cd2baf</guid><dc:creator>GM202604016252</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/65896?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65896/ground-connection-in-simulating-three-phase-pfc/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;&lt;img style="max-height:317px;max-width:702px;" alt=" " height="317" src="https://community.cadence.com/resized-image/__size/1404x634/__key/communityserver-discussions-components-files/110/Screenshot-2026_2D00_04_2D00_01-1815041.png" width="702" /&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;div&gt;
&lt;p&gt;&lt;/p&gt;
&lt;div&gt;
&lt;p&gt;Hi everyone,&lt;/p&gt;
&lt;p&gt;I&amp;rsquo;m simulating a three‑phase PFC in ORCAD PSPice. The real circuit also includes an input LC filter, which I&amp;rsquo;ve omitted here for simplicity, but the behavior I&amp;rsquo;m seeing is always the same. In my current setup, the Pspice ground reference is connected to the negative node of the rectifier bridge, while the three AC sources have their star point left floating. During simulation, I observe that it is the star point of the generators that &amp;ldquo;moves&amp;rdquo; with respect to ground, while the negative node of the bridge remains fixed because it is tied to the reference. Which is of course normal for my simulation.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;I&amp;rsquo;m wondering whether this behavior is correct. Can this simply be considered a consequence of how the simulator assigns the ground reference, or am I introducing a significant error compared to the real‑world behavior of the circuit? In other words, is it acceptable that the generators&amp;rsquo; star point moves while the rectifier negative stays fixed, or could this lead to unrealistic results?&lt;/p&gt;
&lt;p&gt;Another thing I don&amp;rsquo;t fully understand: if I try the opposite approach&amp;mdash;connecting the ground to the star point of the generator and leaving the bridge negative floating (using a very large resistor like 5 M&amp;Omega; instead of the direct connection)&amp;mdash;the simulation immediately diverges, leaving me with no results. Is there a way to stabilize the simulation in this configuration, or is it inherently problematic?&lt;/p&gt;
&lt;p&gt;My main question is: how can I simulate a circuit in which&amp;nbsp;I connect&amp;nbsp;the ground to the star point of the generator and leave the bridge negative floating?&amp;nbsp;&lt;/p&gt;
&lt;p&gt;My &lt;strong&gt;simulation profile&lt;/strong&gt; is: time transient form 0 to 180ms, starting to save data from 160ms. this time to allow the PFC to stabilyze.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Thanks in advance to anyone who can help clarify this.&lt;/p&gt;
&lt;/div&gt;
&lt;br /&gt;
&lt;p&gt;&lt;/p&gt;
&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Using SMSTP(x, r) for Smoother and Faster Simulations in Allegro PSpice</title><link>https://community.cadence.com/thread/65866?ContentTypeID=0</link><pubDate>Tue, 24 Mar 2026 11:41:07 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:72945fe5-e60f-4b87-bb9e-c3809a253764</guid><dc:creator>IshaS</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/65866?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65866/using-smstp-x-r-for-smoother-and-faster-simulations-in-allegro-pspice/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello everyone,&lt;/p&gt;
&lt;p&gt;If you&amp;#39;re using traditional step functions (like &lt;em&gt;STP&lt;/em&gt; or Heaviside) in PSpice, you&amp;rsquo;ve probably seen issues such as sharp discontinuities, tiny timesteps, slow simulations, and convergence problems.&lt;/p&gt;
&lt;p&gt;To overcome these limitations, Allegro PSpice introduces the&amp;nbsp;SMSTP(x, r)&amp;nbsp;function, which is defined as:&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;SMSTP(x,r)=0.5+0.5&lt;/strong&gt;&lt;strong&gt;&amp;sdot;tanh(r&lt;/strong&gt;&lt;strong&gt;&amp;sdot;x)&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;This gives a smooth transition from 0 &amp;rarr; 1, and the parameter &lt;strong&gt;r&lt;/strong&gt; lets you control the steepness.&lt;br /&gt; Higher &lt;strong&gt;r&lt;/strong&gt; = sharper but still smooth transition.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Advantages of SMSTP in Allegro PSpice:&lt;/strong&gt;&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Simulator-Friendly:&amp;nbsp;It reduces the need for tiny timesteps, thus speeding up simulations.&lt;/li&gt;
&lt;li&gt;Improved Convergence:&amp;nbsp;Smooth transitions help solvers reach solutions more reliably.&lt;/li&gt;
&lt;li&gt;Tunable Behavior:&amp;nbsp;The r&amp;nbsp;parameter&amp;nbsp;controls the steepness and domain of the transition, as shown below:&lt;ul&gt;
&lt;li&gt;r = 2 transition over domain &amp;gt; [-1, 1]&lt;/li&gt;
&lt;li&gt;r = 4 domain &amp;gt; [-0.5, 0.5]&lt;/li&gt;
&lt;li&gt;Higher&amp;nbsp;r&amp;nbsp;values &amp;gt; sharper transitions within narrower domains&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Hope this helps anyone working on switching or behavioral models! If needed, I can share example plots or circuit snippets.&lt;/p&gt;
&lt;p&gt;Happy Learning!!&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>How to add the .net file provided by EPC for simulation</title><link>https://community.cadence.com/thread/65823?ContentTypeID=0</link><pubDate>Tue, 10 Mar 2026 09:52:49 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0c33cedd-6219-4a65-b1e6-1d963c83d52f</guid><dc:creator>KW202603107421</dc:creator><slash:comments>3</slash:comments><comments>https://community.cadence.com/thread/65823?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65823/how-to-add-the-net-file-provided-by-epc-for-simulation/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;When simulating the LMG1210, I want to use real GaN switches in the simulation. However, for models like the EPC2204, the manufacturer only provides a .net file. After changing the file extension to .lib, capitalizing .subckt and .ends, and appending EPC2204A, the simulation model still cannot be read.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Exporting parts to capture library not working as expected</title><link>https://community.cadence.com/thread/65802?ContentTypeID=0</link><pubDate>Tue, 03 Mar 2026 19:16:47 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2006ab24-ce63-4faf-8749-71774759801e</guid><dc:creator>cabala</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/65802?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65802/exporting-parts-to-capture-library-not-working-as-expected/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I am sure some variant of this question has been asked but I don&amp;#39;t see anything quite applicable when searching the forum. I have been using OrCAD PSpice for like 15 years on and off again and I swear the process to import models, associate them with a symbol and proceed to use them in a simulation has never been improved.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;We only use OrCAD for the PSpice functionality and do not create boards, etc.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;What I&amp;#39;d really like to understand is how to replicate model libraries and capture libraries similar to the pre-packaged ones included at install (multiple models and parts per library).&lt;/p&gt;
&lt;p&gt;Here are the steps I would think should work (but don&amp;#39;t).&amp;nbsp;&lt;/p&gt;
&lt;p&gt;1. Open PSpice Model Editor and create a new blank library (e.g., BJTS.lib)&lt;/p&gt;
&lt;p&gt;2. Import new model using Model -&amp;gt; Import and select whatever model downloaded from manufacturer, etc&lt;/p&gt;
&lt;p&gt;3. Export to Capture library using File -&amp;gt; Export to Capture Part Library and associate part with a symbol&lt;/p&gt;
&lt;p&gt;4. In Capture, add new BJTS.OLB library, choose part and add to simulation&lt;/p&gt;
&lt;p&gt;5. Add the BJTS.lib as an include file and simulate&lt;/p&gt;
&lt;p&gt;This works until I try to add another model. One would think you just open the model library, import new model, then re-export to capture library. Update design cache if needed or delete the capture library and re-add it. However, the only capture part ever available is the very first one I added. There are no errors during the process and when I export to capture library after adding a new model, I see all the parts in the associate symbol dialogue box. They are associated with symbols, and the event logger says everything passed with zero errors or warnings. But still, only one part in the capture library. If I repeat the process, it says there are already symbols associated with the parts. So again, it seems to be working but in Capture there is only one part shown in the olb.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;I really don&amp;#39;t understand what I am doing wrong here. I can create an individual library for each part and that works but I&amp;#39;d really like to make an all-in-one library for various part types that can be shared with colleagues.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Any advice or corrections would be greatly appreciated. Thanks!&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Has anyone simulated the AMC3301?</title><link>https://community.cadence.com/thread/65773?ContentTypeID=0</link><pubDate>Wed, 25 Feb 2026 06:27:52 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:74ab6bc1-3acd-45ea-a026-0c1153ceee51</guid><dc:creator>deanv</dc:creator><slash:comments>3</slash:comments><comments>https://community.cadence.com/thread/65773?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65773/has-anyone-simulated-the-amc3301/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I have followed the data sheet examples and am getting nothing but errors.&amp;nbsp; I am a new PSpice for TI user.&amp;nbsp; I tried using Google for help.&amp;nbsp; It did help find a few mistakes but overall, it did not help.&amp;nbsp; Is there a reference design that uses this part?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>LMR51625Y Buck converter simulation Too slow</title><link>https://community.cadence.com/thread/65757?ContentTypeID=0</link><pubDate>Wed, 18 Feb 2026 17:27:02 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:808d7adb-5566-4ea3-ada1-03d84de193d9</guid><dc:creator>SS202602185019</dc:creator><slash:comments>3</slash:comments><comments>https://community.cadence.com/thread/65757?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65757/lmr51625y-buck-converter-simulation-too-slow/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;&lt;span&gt;&amp;quot;Hey, I&amp;rsquo;m running a simulation with the attached circuit and config, but it&amp;rsquo;s running incredibly slow. I&amp;rsquo;ve set the&amp;nbsp;&lt;/span&gt;&lt;b data-path-to-node="4" data-index-in-node="116"&gt;Run To Time&lt;/b&gt;&lt;span&gt;&amp;nbsp;to&amp;nbsp;&lt;/span&gt;&lt;b data-path-to-node="4" data-index-in-node="131"&gt;50ms&lt;/b&gt;&lt;span&gt;&amp;nbsp;with a&amp;nbsp;&lt;/span&gt;&lt;b data-path-to-node="4" data-index-in-node="143"&gt;Maximum Step Size&lt;/b&gt;&lt;span&gt;&amp;nbsp;of&amp;nbsp;&lt;/span&gt;&lt;b data-path-to-node="4" data-index-in-node="164"&gt;100ns&lt;/b&gt;&lt;span&gt;. That&amp;rsquo;s 500,000 steps minimum, and it&amp;#39;s taking forever. Does the step size need to be this granular, or is there something in the circuit causing a convergence bottleneck?&amp;quot;&lt;/span&gt;&lt;img alt="&amp;quot;Hey, I&amp;rsquo;m running a simulation with the attached circuit and config, but it&amp;rsquo;s running incredibly slow. I&amp;rsquo;ve set the Run To Time to 50ms with a Maximum Step Size of 100ns. That&amp;rsquo;s 500,000 steps minimum, and it's taking forever. Does the step size need to be this granular, or is there something in the circuit causing a convergence bottleneck?&amp;quot;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/110/Screenshot-2026_2D00_02_2D00_18-224041.png" /&gt;&lt;img src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/110/pastedimage1771435319832v2.png" alt=" " /&gt;&lt;span&gt;&amp;nbsp;, This simulation is after 5 Minutes&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Hi Pspice team, I am getting the follwoing error even after configuration files added.</title><link>https://community.cadence.com/thread/65721?ContentTypeID=0</link><pubDate>Mon, 09 Feb 2026 12:23:50 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8e0cbc93-dd51-4823-8cc2-3cfc3a749b83</guid><dc:creator>SK202602095340</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/65721?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65721/hi-pspice-team-i-am-getting-the-follwoing-error-even-after-configuration-files-added/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;How to fix this error.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;INFO(ORCAP-2191): Creating PSpice Netlist&lt;br /&gt;INFO(ORNET-1041): Writing PSpice Flat Netlist c:\cadence\spb_23.1\tools\pspice\user_lib\lm741-pspicefiles\lm741_test-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net&lt;br /&gt;INFO(ORNET-1169): Unable to open the property mapping file: C:\Cadence\SPB_23.1\tools\PSpice\Librarydevparam.txt. To resolve this problem, ensure that PSpice.ini exists at the correct location. After that check Library Path in simulation settings contains &amp;lt;installation-path&amp;gt;/tools/pspice/library path and then create the netlist again.&lt;br /&gt;INFO(ORNET-1162): Unable to create design property file.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>GLAPLACE XFORM Syntax Recommendation</title><link>https://community.cadence.com/thread/65711?ContentTypeID=0</link><pubDate>Wed, 04 Feb 2026 17:28:50 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b4394e84-5803-4af6-88a7-b693be7b1263</guid><dc:creator>cabala</dc:creator><slash:comments>3</slash:comments><comments>https://community.cadence.com/thread/65711?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65711/glaplace-xform-syntax-recommendation/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi all, I am looking to see if anyone has a recommendation on how to enter this s-domain polynomial into the XFORM property field more compactly?&amp;nbsp;&lt;/p&gt;
&lt;p&gt;(1.76633807e-28*s*s*s*s*s*s*s + 4.37752348e-24*s*s*s*s*s*s + 2.21287946e-20*s*s*s*s*s + 1.63859923e-16*s*s*s*s + 4.51408684e-13*s*s*s + 1.45284939e-9*s*s + 1.42274997e-6*s + 1.19109226e-3) / (-2.49510738e-29*s*s*s*s*s*s*s*s + 3.28470008e-24*s*s*s*s*s*s*s + 1.36672855e-20*s*s*s*s*s*s + 2.41372502e-16*s*s*s*s*s + 6.79605490e-13*s*s*s*s + 4.23416528e-9*s*s*s + 6.15007649e-6*s*s + 6.30604299e-3*s + 1)&lt;/p&gt;
&lt;p&gt;It&amp;#39;s an 8th order polynomial curve fit for an impedance model. It has been tested and works.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;I tried to create .PARAM statement in an include file for &amp;quot;num&amp;quot; and &amp;quot;den&amp;quot; but it didn&amp;#39;t like the &amp;#39;s&amp;#39; variable which makes sense but the above is super cumbersome. Is there a way to define other properties and have XFORM reference that?&lt;/p&gt;
&lt;p&gt;Thanks!&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Test Your Simulation Skills !!</title><link>https://community.cadence.com/thread/65490?ContentTypeID=0</link><pubDate>Mon, 24 Nov 2025 14:32:34 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6c67ce3d-2cbd-41e6-ad4a-cd6681c0abc7</guid><dc:creator>IshaS</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/65490?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65490/test-your-simulation-skills/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Which simulation type is best for analyzing distortion and harmonics in PSpice A/D Analysis?&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;img style="max-height:480px;max-width:640px;" alt=" " src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/110/Screenshot_5F00_quiz1_2D00_min_2D00_min.png" /&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;FFT with DC&amp;nbsp;Sweep&lt;/li&gt;
&lt;li&gt;FFT with transient analysis&lt;/li&gt;
&lt;li&gt;FFT with AC Sweep&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;&amp;nbsp;Share Inputs !!&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>How to import PSpice for TI library in Capture 24.1</title><link>https://community.cadence.com/thread/65432?ContentTypeID=0</link><pubDate>Wed, 05 Nov 2025 20:39:45 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:30270eb7-78ad-470a-89b8-b21d58837f6c</guid><dc:creator>GM202501062717</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/65432?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65432/how-to-import-pspice-for-ti-library-in-capture-24-1/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello,&lt;/p&gt;
&lt;p&gt;In 17.4, there used to be a very easy method to include PSpice for TI libraries and symbols in the full commercial Capture Editor. Now in 24.1, I cannot figure out how to add the PSpice for TI models into the new part search. While it is nice to be able to sync ultralibrarian and other databases, I am very frustrated that I have two installs, PSpice for TI and Capture CIS 24.1, but cannot get the models synced across simulators. I have tried importing nom_pspti.lib into my configuration files, which did not work.&lt;/p&gt;
&lt;p&gt;Any suggestions here would be greatly appreciated. Thank you!&lt;/p&gt;
&lt;p&gt;Gerasimos&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Pspice would develop the new feature: Smith chart? or Develop the Python Interface for data analysis?</title><link>https://community.cadence.com/thread/65428?ContentTypeID=0</link><pubDate>Wed, 05 Nov 2025 05:36:15 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3878cb75-d2c4-416c-b2e3-1d11fcc18a3c</guid><dc:creator>Zhuang Ma</dc:creator><slash:comments>2</slash:comments><comments>https://community.cadence.com/thread/65428?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65428/pspice-would-develop-the-new-feature-smith-chart-or-develop-the-python-interface-for-data-analysis/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I have a new idea: Smith chart? It refert to ABM Model study?&lt;/p&gt;
&lt;p&gt;G-ABM model, E-ABM model. It means we have lots of analysis in the circuit&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Measurement Syntax - Failing Simulation</title><link>https://community.cadence.com/thread/65389?ContentTypeID=0</link><pubDate>Tue, 28 Oct 2025 13:30:23 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e8d257e0-3e03-406b-9eaf-c35dd9c106bd</guid><dc:creator>WM202510282226</dc:creator><slash:comments>3</slash:comments><comments>https://community.cadence.com/thread/65389?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65389/measurement-syntax---failing-simulation/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello,&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;I am wanting to find the time at which when the difference between two voltages is less than a specified value.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;My initial take (below) was this using google AI, but that doesn&amp;#39;t work, and I find the documentation exceptionally unhelpful. At least for Orcad 17.2.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;.MEAS TRAN res4 FIND time WHEN V(Vin)-V(Vb)=0.62&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;This looks LTspice like, so I imagine it&amp;#39;s getting confused. I am running a monte-carlo, so I would like the command to be run each and every time there is a simulation run. So, if there are 100 runs, then there should be 100 data points of a time being given.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>TI SPICE reports "File is read only or used"</title><link>https://community.cadence.com/thread/65273?ContentTypeID=0</link><pubDate>Mon, 29 Sep 2025 08:53:37 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:70b42527-ca2e-4456-a4d8-7506943a65ce</guid><dc:creator>FL20250929850</dc:creator><slash:comments>2</slash:comments><comments>https://community.cadence.com/thread/65273?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65273/ti-spice-reports-file-is-read-only-or-used/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I am using TI SPICE and try to run a simulation which works for the initial downloaded TI package (TL431). I can start the simulation as it it was provided by TI download.&lt;/p&gt;
&lt;p&gt;But I can not save or change the simulation profile or schematic: Message is following&lt;/p&gt;
&lt;p&gt;- tran is read only: can not update&lt;/p&gt;
&lt;p&gt;- schematic is read only&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;In general it seems that the whole project is read only.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;How can I change it from read only to editable?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>How to get superimposition of impulse with  double exponential decaying sine waveform</title><link>https://community.cadence.com/thread/65221?ContentTypeID=0</link><pubDate>Wed, 17 Sep 2025 10:01:59 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:fd0313dc-f7e3-4a34-9054-fcd8afa96aa9</guid><dc:creator>KM202509171147</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/65221?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65221/how-to-get-superimposition-of-impulse-with-double-exponential-decaying-sine-waveform/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I used two independent&amp;nbsp;dou&lt;img style="max-height:480px;max-width:640px;" alt=" " src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/110/Screenshot-2025_2D00_09_2D00_17-153139.png" /&gt;ble exponential decaying sine sources in series using exp source with unit pulse source , i am unable to get superimposed impulse with double eponential decaying sine waveform.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>How to disable sections of OrCAD Capture schematics so they are not simulated?</title><link>https://community.cadence.com/thread/65218?ContentTypeID=0</link><pubDate>Wed, 17 Sep 2025 09:33:12 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3d089796-9d36-44c2-8c1e-44515875029d</guid><dc:creator>YP202407316539</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/65218?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65218/how-to-disable-sections-of-orcad-capture-schematics-so-they-are-not-simulated/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p data-start="158" data-end="280"&gt;In PSPICE, is there a way to run a simulation on only a portion of the circuit without deleting the rest?&lt;/p&gt;
&lt;p data-start="282" data-end="628"&gt;What I&amp;rsquo;d like to do is keep the full schematic as it is, but selectively disable certain components or sections of the circuit so that they are ignored during simulation.&lt;/p&gt;
&lt;p data-start="282" data-end="628"&gt;In other words, I don&amp;rsquo;t want to remove them from the schematic; I just want to turn them off temporarily and run the simulation on the remaining active parts of the circuit.&lt;/p&gt;
&lt;p data-start="630" data-end="699"&gt;Is there a feature or recommended method to achieve this in PSPICE?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>How to Pre-Assign Traces to Different Plots in PSPICE Before Running?</title><link>https://community.cadence.com/thread/65216?ContentTypeID=0</link><pubDate>Wed, 17 Sep 2025 09:20:27 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0792e3b0-d8a5-4456-b99f-2702df91b53f</guid><dc:creator>YP202407316539</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/65216?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65216/how-to-pre-assign-traces-to-different-plots-in-pspice-before-running/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p data-start="96" data-end="184"&gt;In PSPICE, I want to separate multiple traces into two different plots.&lt;/p&gt;
&lt;ul data-start="186" data-end="656"&gt;
&lt;li data-start="186" data-end="399"&gt;
&lt;p data-start="188" data-end="399"&gt;&lt;strong data-start="188" data-end="206"&gt;Current method&lt;/strong&gt;: I draw the circuit, place the markers, &lt;em&gt;Run PSpice&lt;/em&gt;, and when the Probe window opens, I click &lt;em data-start="300" data-end="320"&gt;Add Plot to Window&lt;/em&gt;. Then I manually copy traces from one plot and paste them into the new plot.&lt;/p&gt;
&lt;/li&gt;
&lt;li data-start="400" data-end="656"&gt;
&lt;p data-start="402" data-end="656"&gt;&lt;strong data-start="402" data-end="420"&gt;Desired method&lt;/strong&gt;: Before &lt;em&gt;Run PSpice&lt;/em&gt;&amp;nbsp;(i.e., before the Probe window opens), I&amp;rsquo;d like to assign each marker to a specific plot when placing it. That way, once I run the simulation, the traces are automatically organized into their designated plots.&lt;/p&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;p data-start="658" data-end="690"&gt;Is there a way to set this up?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>PSPICE for TI - TPS2662x - Fixed OVP</title><link>https://community.cadence.com/thread/65156?ContentTypeID=0</link><pubDate>Wed, 03 Sep 2025 15:31:53 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:54bb6a22-306b-4f9d-bf1b-f339b47067ee</guid><dc:creator>Pete5</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/65156?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/65156/pspice-for-ti---tps2662x---fixed-ovp/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;i am trying to simulate the ovp limit of the TPS2662, but it seems that even if i try and set it via the voltage divider the ovp is fixed at about 30V.&lt;/p&gt;
&lt;p&gt;Here is my circuit for setting the ovp to 50V:&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/110/pastedimage1756913308595v1.png" alt=" " /&gt;&lt;br /&gt;I also tried disabling the ovp and uvp:&lt;br /&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/110/pastedimage1756913371659v2.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;But with both circuits the output voltage and output current is basically 0. But if i set the input voltage to 30V the circuit works. Did i do something wrong or is the simulation model wrong?&lt;br /&gt;&lt;br /&gt;Thanks a lot!&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Getting Error ORPSIM-15108 on trying to simulate my project</title><link>https://community.cadence.com/thread/64939?ContentTypeID=0</link><pubDate>Fri, 11 Jul 2025 15:56:13 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c0d8b0b4-ba2d-4b27-9ca3-d6265a6e3746</guid><dc:creator>GR202506302211</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/64939?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/64939/getting-error-orpsim-15108-on-trying-to-simulate-my-project/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello&lt;/p&gt;
&lt;p&gt;I&amp;#39;m trying to simulate a circuit with Orcad Capture CIS (30 day tryal version) and the part AD8250.&lt;/p&gt;
&lt;p&gt;I imported the AD8250 Spice model from the .cir file and created the .olb file&amp;nbsp;&lt;/p&gt;
&lt;p&gt;I was able to place the AD8250 part but i already have this drc:&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&amp;quot;WARNING(ORCAP-2445): Instance U4: SCHEMATIC1, PAGE1 (2.20, 4.00). not found in the configured libraries&amp;quot;&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;Then if i try to run a simulation then i have this error:&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&amp;quot;ERROR(ORPSIM-15108): Subcircuit AD8250 used by X_U4 is undefined&amp;quot;&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;I tryed to follow the steps below without success:&lt;/p&gt;
&lt;p&gt;&lt;a href="https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000050ZKEAY&amp;amp;pageName=ArticleContent"&gt;Troubleshooting OrCAD Capture PSpice Simulation Flow Errors&lt;/a&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;The AD8250.ind was generated so it should not be a write access permission issue&lt;/p&gt;
&lt;p&gt;Any ideas to solve that ?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>