PSpice - Recent Threads

Your access to On-Demand Webinar : From Wall to Rail – Turning Rules of Thumb into Proof

Renu Vibha — Wed, 29 Jul 2026 05:50:12 GMT

Rules of thumb don't pass safety reviews; proof does.

This webinar demonstrates constraint-driven flyback design in Cadence’s Allegro X Design Platform and PSpice.

See how to verify hot-loop geometry, isolation spacing, and startup behavior before you build hardware.

For more details , check From Wall to Rail – Turning Rules of Thumb into Proof | Cadence

Modeling Schottky Diodes in PSpice – Understanding IS and N Parameters

IshaS — Tue, 28 Jul 2026 09:32:41 GMT

Schottky diodes are indispensable part of modern hardware design. Their low forward voltage drop (typically 0.2–0.45 V versus 0.6–0.7 V for a standard PN junction) and near-zero reverse recovery time make them go-to choice in high-frequency switching power supplies, RF signal detection, OR-ing circuits, and flyback clamp networks. Wherever efficiency, speed, or tight voltage headroom matters, a Schottky is usually in the signal path.

But selecting the right device is only half the job. Simulating it accurately is the other half and that's where most designs quietly go wrong.

In PSpice, a Schottky diode's behavior is governed primarily by two model parameters: IS (reverse saturation current) and N (ideality factor). These two values define the entire shape of the I-V curve. Get them right, and your simulation predicts forward voltage drop, power dissipation, and switching behavior with confidence. Get them wrong - which happens whenever you use an unverified default model - and every downstream calculation built on that simulation is off including thermal margins, efficiency estimates and gate drive timing.

This post walks through how to tune IS and N in PSpice using nested DC sweeps, so your simulation matches the datasheet and holds up on the bench.

The diode current is governed by the equation:
I = IS (e^(V / (N·Vt)) − 1)

This indicates that both IS and N play an important role in determining the forward voltage characteristics.

IS (Reverse Saturation Current): Determines where along the voltage axis the I-V curve sits. In Schottky models, IS is typically several orders of magnitude larger than in standard PN junctions — often in the μA to mA range — which is the physical reason Schottky diodes conduct at a lower forward voltage. A lower IS shifts the curve to the right, increasing Vf for a given forward current. A higher IS shifts it left, reducing Vf.

N (Ideality Factor): Controls the steepness of the exponential rise. An ideal diode has N = 1; real Schottky devices typically fall between 1.0 and 2.2 depending on the junction technology and operating region. A higher N flattens the curve — you need more voltage to drive the same current — and also makes the forward voltage more sensitive to temperature variation.

Together, IS sets the operating point and N shapes the curve around it. Both need to be calibrated to the actual device for the simulation to be trustworthy.

Simulation Steps:

Perform a DC sweep analysis on a forward-biased circuit.

Use Parametric sweeps to vary IS and N independently.
Example ranges:
- IS: 3e-04 to 3e-08
- N: 2.2 to 3
Observe resulting changes in forward voltage and current characteristics.

Effect of IS (Reverse Saturation Current):

- Forward voltage drop can be tuned by modifying IS.
- A lower IS results in a higher forward voltage for the same current.

Effect of N (Ideality Factor):
- Controls the slope of the I-V curve.
- Changing N modifies exponential behavior and deviation from ideal characteristics.

This approach helps in accurately matching the diode model to real device behavior and achieving reliable simulation results.

Have you run into a Schottky (or any diode) model that just wouldn’t match the datasheet or your bench data?
Drop your experience in the comments – what device, what mismatch, and how you resolved it.

Happy Learning!!

Associate psice model greyed out

Shashank — Tue, 21 Jul 2026 16:35:43 GMT

OrCAD X Capture 24.1.
Created Project A without selecting Enable PSpice Simulation.
Created Project B with Enable PSpice Simulation selected.
Placed the same SamacSys Library Loader component in both projects.
In Project A, Associate PSpice Model is grayed out.
In Project B, Associate PSpice Model is enabled.
Since Simulation Profile can still be created in both Projects , I am unsure why only Associate PSpice Model is disabled.
Is this expected behavior in OrCAD X Capture 24.1?
Is there a supported way to enable Associate PSpice Model in an existing project created without Enable PSpice Simulation, or is creating a new PSpice-enabled project required?
Is there any project setting that controls the availability of Associate PSpice Model?

RE: Associate psice model greyed out

Shashank — Thu, 23 Jul 2026 11:24:11 GMT

Hi Isha,

Thanks for the reply!

In custom libraries(manually created) and online downloaded libraries this option is greyed out.

Is there any way to change this to PSpice specific project?

RE: Associate psice model greyed out

IshaS — Thu, 23 Jul 2026 11:07:32 GMT

Hi Shashank,

This appears to be expected behavior.
When a project is created without selecting "Enable PSpice Simulation", the project is treated as a standard schematic project and certain PSpice-specific commands are disabled.
One of those commands seems to be Associate PSpice Model. Even though Capture may still allow creation of a Simulation Profile later, the project itself was not initialized with the full PSpice simulation configuration, so some simulation-related UI options remain unavailable.

which components do you see as disabled?

PSpice Special Components: Print1, Print2 and PRINTDGTLCHG

AyushD — Tue, 07 Jul 2026 16:41:44 GMT

Print1:

Use this component to insert .PRINT command in your simulation. This component enables you to print voltage at node in simulation output (.out) file.

You need to configure one or more parameters on this symbol instances from following list to use in simulation flow.

Analysis Type: Assign any value to one of the variables AC/DC/TRAN, depending upon the analysis you are performing. For example if your simulation profile is configured for Transient Analysis you should set TRAN property value as 1.
Functions: You can use following special function on output nodes
- DB
- PHASE
- REAL
- MAG
- IMAG
You can use one or more of the parameters at a time. To select these you need to assign any value to these parameter, say, 1. For example, if you have set DB and PHASE values to 1 on symbol instance and this component is connected to node VOUT, it will print following in output file:
DB of Voltage at VOUT node
PHASE of Voltage at VOUT node

Print2:

PRINT2 performs the same function as PRINT1, only difference being this component should be used for differential voltage between two nodes.

PRINTDGTLCHG:

Use this component for digital nodes. It lists every change of state for a given node in the output file. You need not specify any parameter on this symbol instance.

使用 PSpice-for-TI时，显示这个芯片没有在已配置的库中找到，我尝试在Simulation Settings中配置，

WZ202606154651 — Mon, 15 Jun 2026 14:22:10 GMT

使用 PSpice-for-TI时，我在我自己创建的例程中使用LMR33630ADDA_TRANS等芯片时，会出现一个警告，显示这个芯片没有在已配置的库中找到，我尝试在Simulation Settings中配置，并没有什么用，并且仿真结果异常

RE: 使用 PSpice-for-TI时，显示这个芯片没有在已配置的库中找到，我尝试在Simulation Settings中配置，

IshaS — Wed, 17 Jun 2026 10:35:54 GMT

Can you try this:

配置仿真设置

在 PSpice 设计界面中，点击顶部菜单栏的 PSpice > Edit Simulation Profile。
点击顶部的 Configuration Files 标签页。
在左侧面板中选择 Category > Library。

RE: Exporting PSPICE netlist with Subckt parameters

oldmouldy — Thu, 04 Jun 2026 16:01:38 GMT

I have the same settings and using 25.1.s030. It doesn't look like I can attach an archived project to try.

Exporting PSPICE netlist with Subckt parameters

SC202412036016 — Wed, 03 Jun 2026 20:44:16 GMT

I am trying to export a PSPICE netlist of a simple subcircuit where I have to pass in parameters, however parameter definition is happening after ENDS, instead of the top line where the subcircuit is being defined. There is a .PARAMS in the subckt line however the actual parameter (lval) is showing up right at the end. Any ideas on where the issues may be?

I cannot seem to attach a screenshot of the template settings, but if this works for anyone would be great if you can send a screenshot of the template settings where the ParamList is displayed at the top.

1. To extract the netlist I go to Tools > Create Netlist

2. Here is the output:

* source BLOCK_AOL
.SUBCKT Aol_Block InN InP OutN OutP PARAMS :
G_G1 OUTP OUTN INP INN -1u
L_L1 N00976 OUTN {LVAL} TC=0,0
R_R2 N00976 OUTP 1M TC=0,0
.ENDS Aol_Block
.PARAM lval=1n

RE: Exporting PSPICE netlist with Subckt parameters

SC202412036016 — Thu, 04 Jun 2026 14:39:57 GMT

Hi - I do have that checked and so it does export the netlist, however the issue is that the PARAMS list on the subcircuit line is blank and instead the parameters are placed on the last line after the .END statement. Unfortunately I cannot seem to upload screenshots of my Create Netlist settings so will describe it here.

On the PSPICE tab, the following are checked:

Create Hierarchical Format Netlist

Create SubCircuit Format Netlist >> Descend

Compatibility Mode (16.2 and Prior Releases)

I then click on Settings. In the Hierarchical PSPICE Netlist Settings this is what I have :

Sub-circuit Call: X_<RefDes> <PinList> <SubcktName> PARAMS : <ParamList>

ParamList Element Definition: <Param> = <Value>

Sub-Circuit Header: .SUBCKT <SubcktName> <PinList> PARAMS : <ParamList>

ParamList Element Definition: <Param> = <Value>

Param Usage Reference: {Param>}

Sub-circuit Ends: .ENDS <SubcktName>

If one of you is able to actually get the parameter values exported on the sub-circuit line, please let me know if your settings are different from what I have above.

Thanks.

RE: Exporting PSPICE netlist with Subckt parameters

oldmouldy — Thu, 04 Jun 2026 13:29:36 GMT

Try the following: Select the DSN file entry in the Project Manager pane. Then Tools>Create Netlist, PSpice tab, enable Create SubCircuit Format Netlist and left-click>OK

RE: Exporting PSPICE netlist with Subckt parameters

IshaS — Thu, 04 Jun 2026 06:29:36 GMT

Hi SC202412036016

Can you please try:

* source BLOCK_AOL
.SUBCKT Aol_Block InN InP OutN OutP PARAMS: LVAL=1u
G_G1 OUTP OUTN INP INN -1u
L_L1 N00976 OUTN {LVAL} TC=0,0
R_R2 N00976 OUTP 1M TC=0,0
.ENDS Aol_Block
.PARAM lval=1n

Share your insights how it goes at your end.

RE: Persistent netlisting error

IshaS — Thu, 04 Jun 2026 06:27:14 GMT

Hi AG202606016357,

Can you please try below:

copy the attached devparam.txt file at the <cdns_inst_dir>/tools/pspice/library location.
/cfs-file/__key/communityserver-discussions-components-files/110/devparam.txt

Open your simulation settings:
Check the library path in the Simulation Settings window as shown in the following snapshot. In Capture, go to PSpice > Edit simulation profile > Configuration Files > Library and check the Library Path value. It should point to <cdns_inst_dir>/tools/pspice/library.

Try this and share your insights how it goes at your end.

Persistent netlisting error

AG202606016357 — Mon, 01 Jun 2026 12:07:33 GMT

Hello,

I'm using "PSpice for TI" to simulate a DCDC converter implementing a specific TI PWM controller (hence the selection of the simulation tool).

My schematic is drawn and seems correct. Still, when I launch the netlist generation, I get the following error message:

"ERROR(ORCAP-15065): There are netlisting errors.

Check the session log."

In the session log, I find:

"INFO(ORNET-1041): Writing PSpice Flat Netlist \\xxx\yyy\SCHEMATIC1\SCHEMATIC1.net
INFO(ORNET-1169): Unable to open the property mapping file: devparam.txt. To resolve this problem, ensure that PSpice.ini exists at the correct location. After that check Library Path in simulation settings contains <installation-path>/tools/pspice/library path and then create the netlist again.
INFO(ORNET-1162): Unable to create design property file"

I completed the proposed checks and everything is OK.

I gave a try with a very simple schematic (1 DC source, 1 ideal R and 1 ideal C). I got the exact same error.

How can I solve this error?

What should I do?

Thanks for helping me.

Pspice simulation crashing

JB20250410478 — Fri, 25 Apr 2025 11:05:28 GMT

Hi,
I'm doing a project and need some simulations.
I've succesfully ran simulation on schematic1, but when I try to simulate schematic2 there are just a bunch of error/crash messages.
Could this be because the schematic is to "advanced" or what could be the problem?
I've already tried to reinstall PSpife for TI, but to no avail, same proiblem as before, I get an error saying the simulation crashed and then errors saying the RPC-server is not availible, but when I try to simulate the circuit in schematic1 it works?

Please help!

PSpice Special Component: Watch1

AyushD — Sun, 31 May 2026 19:15:05 GMT

.WATCH command enables user to observe voltage at node in simulation status windows while simulation is in progress.

Attach this part (WATCH1) at node or net which you will like to observe during the simulation. After this, you need to define following three parameters on symbol instance:

Analysis: Assign the one of the following three values depending upon the type of analysis being performed:
DC
AC
TRAN

HI: Assign a numeric value to define upper limit of voltage
LO: Assign a numeric value to define lower limit of voltage

Simulator pauses if voltage at node is outside of range defined by HI and LO.

Unable to Upload Images

MrTF — Mon, 04 May 2026 16:26:34 GMT

Dear all,

I have tried several times to upload an image from my simulation in order to post a question.

Unfortunately, this has not been possible so far. Each time, I receive a message advising me to contact the administrator.

Could you please let me know how to proceed or whom I should contact to resolve this issue?

Thank you in advance for your support.

RE: Unable to Upload Images

Zhifeng Jin — Thu, 07 May 2026 15:28:15 GMT

https://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/63326/why-i-can-t-insert-pictures-from-my-computer

The dedicated section for feedback, suggestions and questions here is nothing but a mere formality.

As one of the world’s top three EDA companies, it really ought to benchmark and learn from Siem*ns EDA in terms of forum operation and community maintenance.

RE: Unable to Upload Images

MrTF — Wed, 06 May 2026 20:58:46 GMT

Again impossible:

An error occurred. Please try again or contact your administrator.

RE: Unable to Upload Images

rg13 — Wed, 06 May 2026 18:20:59 GMT

Let us check on that. Try posting the image and your question to answer to this thread.

RE: Efficient Method to Perform Temperature Sensitivity Analysis and Rank Dominant Components in PSpice

IshaS — Fri, 01 May 2026 11:47:13 GMT

Hi MrTF,

Can you help me with which performance metric are you primarily analyzing for temperature sensitivity in this design?
By any chance have you tried Monte Carlo analyses with temperature‑dependent parameters in PSpice?

Efficient Method to Perform Temperature Sensitivity Analysis and Rank Dominant Components in PSpice

MrTF — Thu, 30 Apr 2026 15:43:57 GMT

I am working on a precision analog circuit and I want to assess temperature sensitivity and identify which components dominate performance variation due to temperature in an efficient and automated way.

My objective is not simply to observe output variation of a specific performance metric versus temperature, but to:

Quantify the sensitivity of a performance metric (e.g., output current, impedance, or noise) with respect to temperature
Attribute this variation to individual components (R, L, C, coupling factors, parasitics, etc.)
Rank components based on their contribution to the overall temperature-induced variation

One approach I considered is to encode temperature effects as equivalent tolerances (i.e., mapping TC-induced drift into % variation) and then perform a standard sensitivity or worst-case analysis. However, this would require maintaining two versions of the circuit (nominal vs “temperature-perturbed”), which is not practical or scalable.

To clarify, I am not referring to a simple global temperature sweep or single-parameter variation. I am looking for a method that enables systematic decomposition of temperature effects across all components.

Is there a rigorous and efficient workflow in PSpice/Cadence to:

perform sensitivity analysis with respect to temperature and
automatically identify and rank the dominant contributors?

Any guidance on built-in features I may miss would be highly appreciated.

Model stepping in PSpice

IshaS — Thu, 30 Apr 2026 16:38:48 GMT

Starting with SPB 25.1, PSpice introduces model stepping, which allows multiple models of the same component to be simulated in a single run and compared directly in the Probe window. All results are stored in one data file, making side‑by‑side analysis simple and efficient.

This is done using the. modelstep directive. For example, as shown in the following image, for the given circuit, a .modelstep statement has been defined as:

@PSpice:

.modelstep STPSC10065D MUR1560

Now, tool will simulate the design with both the PSpice models for D1 as defined in the above statement (STPSC10065D and MUR1560).

When the simulation is run, PSpice automatically steps through both models and displays their results together in the Probe window. This makes it easy to compare waveforms and performance and select the most suitable device. The Probe output also shows the total job time for all stepped models.

Try this and share your insights!

Happy Learning !!

OP467 Component - Simulation Model Issue

MrTF — Tue, 14 Apr 2026 11:07:43 GMT

Dear all,

I am using the OP467 model, which I selected via (Menu)
Place → Component → PSpice Category Model.

During simulation, I receive the following warning:

DRC Type: Electrical
Warning (ORCAP‑2445)
Instance UxD, SCHEMATIC1, PAGE 1 (XXX.xx, XXX.xx),
not found in the configured libraries.

Could someone please clarify:

What exactly does this warning refer to?
Does it imply any potential malfunction or inaccuracy in the simulation results?
Why is the component reported as “not found in the configured libraries,” even though it appears to be located under the CIS Unified Library?
In the model I use there is a parameter with the description "LEVEL 3". To what this parameter refers to?

Any guidance would be greatly appreciated.

Thank you in advance.