PSpice - Recent Threads

Exporting PSPICE netlist with Subckt parameters

SC202412036016 — Wed, 03 Jun 2026 20:44:16 GMT

I am trying to export a PSPICE netlist of a simple subcircuit where I have to pass in parameters, however parameter definition is happening after ENDS, instead of the top line where the subcircuit is being defined. There is a .PARAMS in the subckt line however the actual parameter (lval) is showing up right at the end. Any ideas on where the issues may be?

I cannot seem to attach a screenshot of the template settings, but if this works for anyone would be great if you can send a screenshot of the template settings where the ParamList is displayed at the top.

1. To extract the netlist I go to Tools > Create Netlist

2. Here is the output:

* source BLOCK_AOL
.SUBCKT Aol_Block InN InP OutN OutP PARAMS :
G_G1 OUTP OUTN INP INN -1u
L_L1 N00976 OUTN {LVAL} TC=0,0
R_R2 N00976 OUTP 1M TC=0,0
.ENDS Aol_Block
.PARAM lval=1n

RE: Exporting PSPICE netlist with Subckt parameters

oldmouldy — Thu, 04 Jun 2026 16:01:38 GMT

I have the same settings and using 25.1.s030. It doesn't look like I can attach an archived project to try.

RE: Exporting PSPICE netlist with Subckt parameters

SC202412036016 — Thu, 04 Jun 2026 14:39:57 GMT

Hi - I do have that checked and so it does export the netlist, however the issue is that the PARAMS list on the subcircuit line is blank and instead the parameters are placed on the last line after the .END statement. Unfortunately I cannot seem to upload screenshots of my Create Netlist settings so will describe it here.

On the PSPICE tab, the following are checked:

Create Hierarchical Format Netlist

Create SubCircuit Format Netlist >> Descend

Compatibility Mode (16.2 and Prior Releases)

I then click on Settings. In the Hierarchical PSPICE Netlist Settings this is what I have :

Sub-circuit Call: X_<RefDes> <PinList> <SubcktName> PARAMS : <ParamList>

ParamList Element Definition: <Param> = <Value>

Sub-Circuit Header: .SUBCKT <SubcktName> <PinList> PARAMS : <ParamList>

ParamList Element Definition: <Param> = <Value>

Param Usage Reference: {Param>}

Sub-circuit Ends: .ENDS <SubcktName>

If one of you is able to actually get the parameter values exported on the sub-circuit line, please let me know if your settings are different from what I have above.

Thanks.

RE: Exporting PSPICE netlist with Subckt parameters

oldmouldy — Thu, 04 Jun 2026 13:29:36 GMT

Try the following: Select the DSN file entry in the Project Manager pane. Then Tools>Create Netlist, PSpice tab, enable Create SubCircuit Format Netlist and left-click>OK

RE: Exporting PSPICE netlist with Subckt parameters

IshaS — Thu, 04 Jun 2026 06:29:36 GMT

Hi SC202412036016

Can you please try:

* source BLOCK_AOL
.SUBCKT Aol_Block InN InP OutN OutP PARAMS: LVAL=1u
G_G1 OUTP OUTN INP INN -1u
L_L1 N00976 OUTN {LVAL} TC=0,0
R_R2 N00976 OUTP 1M TC=0,0
.ENDS Aol_Block
.PARAM lval=1n

Share your insights how it goes at your end.

RE: Persistent netlisting error

IshaS — Thu, 04 Jun 2026 06:27:14 GMT

Hi AG202606016357,

Can you please try below:

copy the attached devparam.txt file at the <cdns_inst_dir>/tools/pspice/library location.
/cfs-file/__key/communityserver-discussions-components-files/110/devparam.txt

Open your simulation settings:
Check the library path in the Simulation Settings window as shown in the following snapshot. In Capture, go to PSpice > Edit simulation profile > Configuration Files > Library and check the Library Path value. It should point to <cdns_inst_dir>/tools/pspice/library.

Try this and share your insights how it goes at your end.

Persistent netlisting error

AG202606016357 — Mon, 01 Jun 2026 12:07:33 GMT

Hello,

I'm using "PSpice for TI" to simulate a DCDC converter implementing a specific TI PWM controller (hence the selection of the simulation tool).

My schematic is drawn and seems correct. Still, when I launch the netlist generation, I get the following error message:

"ERROR(ORCAP-15065): There are netlisting errors.

Check the session log."

In the session log, I find:

"INFO(ORNET-1041): Writing PSpice Flat Netlist \\xxx\yyy\SCHEMATIC1\SCHEMATIC1.net
INFO(ORNET-1169): Unable to open the property mapping file: devparam.txt. To resolve this problem, ensure that PSpice.ini exists at the correct location. After that check Library Path in simulation settings contains <installation-path>/tools/pspice/library path and then create the netlist again.
INFO(ORNET-1162): Unable to create design property file"

I completed the proposed checks and everything is OK.

I gave a try with a very simple schematic (1 DC source, 1 ideal R and 1 ideal C). I got the exact same error.

How can I solve this error?

What should I do?

Thanks for helping me.

Pspice simulation crashing

JB20250410478 — Fri, 25 Apr 2025 11:05:28 GMT

Hi,
I'm doing a project and need some simulations.
I've succesfully ran simulation on schematic1, but when I try to simulate schematic2 there are just a bunch of error/crash messages.
Could this be because the schematic is to "advanced" or what could be the problem?
I've already tried to reinstall PSpife for TI, but to no avail, same proiblem as before, I get an error saying the simulation crashed and then errors saying the RPC-server is not availible, but when I try to simulate the circuit in schematic1 it works?

Please help!

RE: Pspice simulation crashing

LC202605041857 — Mon, 01 Jun 2026 09:47:19 GMT

Could this be because the schematic is to "advanced" or what could be the problem?

PSpice Special Component: Watch1

AyushD — Sun, 31 May 2026 19:15:05 GMT

.WATCH command enables user to observe voltage at node in simulation status windows while simulation is in progress.

Attach this part (WATCH1) at node or net which you will like to observe during the simulation. After this, you need to define following three parameters on symbol instance:

Analysis: Assign the one of the following three values depending upon the type of analysis being performed:
DC
AC
TRAN

HI: Assign a numeric value to define upper limit of voltage
LO: Assign a numeric value to define lower limit of voltage

Simulator pauses if voltage at node is outside of range defined by HI and LO.

Unable to Upload Images

MrTF — Mon, 04 May 2026 16:26:34 GMT

Dear all,

I have tried several times to upload an image from my simulation in order to post a question.

Unfortunately, this has not been possible so far. Each time, I receive a message advising me to contact the administrator.

Could you please let me know how to proceed or whom I should contact to resolve this issue?

Thank you in advance for your support.

RE: Unable to Upload Images

Zhifeng Jin — Thu, 07 May 2026 15:28:15 GMT

https://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/63326/why-i-can-t-insert-pictures-from-my-computer

The dedicated section for feedback, suggestions and questions here is nothing but a mere formality.

As one of the world’s top three EDA companies, it really ought to benchmark and learn from Siem*ns EDA in terms of forum operation and community maintenance.

RE: Unable to Upload Images

MrTF — Wed, 06 May 2026 20:58:46 GMT

Again impossible:

An error occurred. Please try again or contact your administrator.

RE: Unable to Upload Images

rg13 — Wed, 06 May 2026 18:20:59 GMT

Let us check on that. Try posting the image and your question to answer to this thread.

RE: Efficient Method to Perform Temperature Sensitivity Analysis and Rank Dominant Components in PSpice

IshaS — Fri, 01 May 2026 11:47:13 GMT

Hi MrTF,

Can you help me with which performance metric are you primarily analyzing for temperature sensitivity in this design?
By any chance have you tried Monte Carlo analyses with temperature‑dependent parameters in PSpice?

Efficient Method to Perform Temperature Sensitivity Analysis and Rank Dominant Components in PSpice

MrTF — Thu, 30 Apr 2026 15:43:57 GMT

I am working on a precision analog circuit and I want to assess temperature sensitivity and identify which components dominate performance variation due to temperature in an efficient and automated way.

My objective is not simply to observe output variation of a specific performance metric versus temperature, but to:

Quantify the sensitivity of a performance metric (e.g., output current, impedance, or noise) with respect to temperature
Attribute this variation to individual components (R, L, C, coupling factors, parasitics, etc.)
Rank components based on their contribution to the overall temperature-induced variation

One approach I considered is to encode temperature effects as equivalent tolerances (i.e., mapping TC-induced drift into % variation) and then perform a standard sensitivity or worst-case analysis. However, this would require maintaining two versions of the circuit (nominal vs “temperature-perturbed”), which is not practical or scalable.

To clarify, I am not referring to a simple global temperature sweep or single-parameter variation. I am looking for a method that enables systematic decomposition of temperature effects across all components.

Is there a rigorous and efficient workflow in PSpice/Cadence to:

perform sensitivity analysis with respect to temperature and
automatically identify and rank the dominant contributors?

Any guidance on built-in features I may miss would be highly appreciated.

Model stepping in PSpice

IshaS — Thu, 30 Apr 2026 16:38:48 GMT

Starting with SPB 25.1, PSpice introduces model stepping, which allows multiple models of the same component to be simulated in a single run and compared directly in the Probe window. All results are stored in one data file, making side‑by‑side analysis simple and efficient.

This is done using the. modelstep directive. For example, as shown in the following image, for the given circuit, a .modelstep statement has been defined as:

@PSpice:

.modelstep STPSC10065D MUR1560

Now, tool will simulate the design with both the PSpice models for D1 as defined in the above statement (STPSC10065D and MUR1560).

When the simulation is run, PSpice automatically steps through both models and displays their results together in the Probe window. This makes it easy to compare waveforms and performance and select the most suitable device. The Probe output also shows the total job time for all stepped models.

Try this and share your insights!

Happy Learning !!

OP467 Component - Simulation Model Issue

MrTF — Tue, 14 Apr 2026 11:07:43 GMT

Dear all,

I am using the OP467 model, which I selected via (Menu)
Place → Component → PSpice Category Model.

During simulation, I receive the following warning:

DRC Type: Electrical
Warning (ORCAP‑2445)
Instance UxD, SCHEMATIC1, PAGE 1 (XXX.xx, XXX.xx),
not found in the configured libraries.

Could someone please clarify:

What exactly does this warning refer to?
Does it imply any potential malfunction or inaccuracy in the simulation results?
Why is the component reported as “not found in the configured libraries,” even though it appears to be located under the CIS Unified Library?
In the model I use there is a parameter with the description "LEVEL 3". To what this parameter refers to?

Any guidance would be greatly appreciated.

Thank you in advance.

RE: OP467 Component - Simulation Model Issue

MrTF — Mon, 20 Apr 2026 06:39:20 GMT

Dear AyushD.

Yes, the warning appears on the "Online DRCs" tab,

Spice simulation is completed without any warnings but I cannot say if it is successful or not if the model is not properly inferred by the simulation engine.

RE: OP467 Component - Simulation Model Issue

AyushD — Thu, 16 Apr 2026 13:01:37 GMT

Are you getting this error in Online DRC ?
Do you get any such error / message in .out file of the PSpice simulation.

Is the simulation run successful ?

RE: Ground connection in simulating three phase PFC

rg13 — Tue, 07 Apr 2026 11:42:14 GMT

You will be contacted via different channel of communication, as this may involve data sharing.

Ground connection in simulating three phase PFC

GM202604016252 — Fri, 03 Apr 2026 09:50:19 GMT

Hi everyone,

I’m simulating a three‑phase PFC in ORCAD PSPice. The real circuit also includes an input LC filter, which I’ve omitted here for simplicity, but the behavior I’m seeing is always the same. In my current setup, the Pspice ground reference is connected to the negative node of the rectifier bridge, while the three AC sources have their star point left floating. During simulation, I observe that it is the star point of the generators that “moves” with respect to ground, while the negative node of the bridge remains fixed because it is tied to the reference. Which is of course normal for my simulation.

I’m wondering whether this behavior is correct. Can this simply be considered a consequence of how the simulator assigns the ground reference, or am I introducing a significant error compared to the real‑world behavior of the circuit? In other words, is it acceptable that the generators’ star point moves while the rectifier negative stays fixed, or could this lead to unrealistic results?

Another thing I don’t fully understand: if I try the opposite approach—connecting the ground to the star point of the generator and leaving the bridge negative floating (using a very large resistor like 5 MΩ instead of the direct connection)—the simulation immediately diverges, leaving me with no results. Is there a way to stabilize the simulation in this configuration, or is it inherently problematic?

My main question is: how can I simulate a circuit in which I connect the ground to the star point of the generator and leave the bridge negative floating?

My simulation profile is: time transient form 0 to 180ms, starting to save data from 160ms. this time to allow the PFC to stabilyze.

Thanks in advance to anyone who can help clarify this.

Using SMSTP(x, r) for Smoother and Faster Simulations in Allegro PSpice

IshaS — Tue, 24 Mar 2026 11:41:07 GMT

Hello everyone,

If you're using traditional step functions (like STP or Heaviside) in PSpice, you’ve probably seen issues such as sharp discontinuities, tiny timesteps, slow simulations, and convergence problems.

To overcome these limitations, Allegro PSpice introduces the SMSTP(x, r) function, which is defined as:

SMSTP(x,r)=0.5+0.5⋅tanh(r⋅x)

This gives a smooth transition from 0 → 1, and the parameter r lets you control the steepness.
Higher r = sharper but still smooth transition.

Advantages of SMSTP in Allegro PSpice:

Simulator-Friendly: It reduces the need for tiny timesteps, thus speeding up simulations.
Improved Convergence: Smooth transitions help solvers reach solutions more reliably.
Tunable Behavior: The r parameter controls the steepness and domain of the transition, as shown below:
- r = 2 transition over domain > [-1, 1]
- r = 4 domain > [-0.5, 0.5]
- Higher r values > sharper transitions within narrower domains

Hope this helps anyone working on switching or behavioral models! If needed, I can share example plots or circuit snippets.

Happy Learning!!

How to add the .net file provided by EPC for simulation

KW202603107421 — Tue, 10 Mar 2026 09:52:49 GMT

When simulating the LMG1210, I want to use real GaN switches in the simulation. However, for models like the EPC2204, the manufacturer only provides a .net file. After changing the file extension to .lib, capitalizing .subckt and .ends, and appending EPC2204A, the simulation model still cannot be read.

RE: How to add the .net file provided by EPC for simulation

GS202603129734 — Thu, 12 Mar 2026 07:33:12 GMT

EPC GaN models often have more than the standard 3 pins (G, D, S). They usually separate the temperature sensor pins or substrate pins.

Open the .lib file with Notepad.

Find the line .SUBCKT. Count how many connections are listed after the component name.

Solution: You need to create a new Symbol (.asy in LTspice) with the number and order of pins exactly matching the list in the .lib file. If you use the default nmos symbol (only 3 pins), the simulator will report an error due to missing connections.