https://community.cadence.com/cadence_technology_forums/pcb-design/en-USTelligent Community 12https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66123/disable-cm-updates-or-audits-during-component-replace-through-tcl/1408834Fri, 03 Jul 2026 13:16:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d74c2228-1166-4a34-9224-d48342b5eb82PatEscherI can confirm, CM flow is enabled capIsCMFlowEnabled delivers 1 So is there a possibility to temporarily turn it off, then do the replace of the components and then turn it on again?I quickly checked the available tcl commands, but did not find a command/method which is selfspeakinghttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66130/don-t-miss-our-live-interactive-upcoming-orcad-x-session-on-july-8th-wednesdayThu, 02 Jul 2026 14:36:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:30a2e6ab-46a3-43dc-a840-65ccc8980d57Renu VibhaCurious about what other users are trying in latest release of OrCAD X—or looking to solve design challenges faster? Join our live, interactive session with Cadence experts and get real-time answers to your toughest PCB design questions. Date : July 8, 2026 at 7:30 – 8:30 PM IST Location : here What’s on the agenda: Cloud Features: Work in shared cloud workspaces, create and manage components, track revisions, control versions of design and collaborate seamlessly. Variants: Create BOM Variants, manage alternate and substitute parts, and export variant.lst file for downstream manufacturing processes. Why you should attend: Get instant answers to your questions See real-world use cases in action Connect and exchange insights with peers Bring your challenges, explore new possibilities, and walk away with actionable insights. Save your spot now and be part of the conversation, register now !https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66115/fanout-of-outer-layer-gnd-smd-pins-to-via-in-pad-in-allegro/1408829Thu, 02 Jul 2026 13:01:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ab284414-6d53-4550-a065-1576b5fe9c20HoangkhoipcbHi BC202603263145 , You can try following this suggestion. It runs on the version OrCAD X PCB Professional Plus 25.1 BR, HoangKhoihttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/66129/how-to-import-a-techfile-through-skillThu, 02 Jul 2026 12:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:724bfde6-78c7-4dad-b6b3-f16d0f02e3c6JuanCRaxlRunBatchDBProgram can be used to import a techfile. Open the design in Allegro X PCB Editor or Package Designer and type skill at the command line: Command > skill The command line changes to the Skill prompt: Skill > The following skill code will create a log file and import a techfile. In the following skill code, replace mytechfile.tcfx with your own techfile name including the .tcfx extension: Skill > axlRunBatchDBProgram("techfile" "techfile -$ -r mytechfile.tcfx %s" ?reloadDB t ?logfile "techfile") Wait while the techfile (apd) runs: The view of the techfile UI will appear. Scroll to view the summary. Close the file. In the database, to exit from the skill prompt, type exit : Skill > exit The Command window changes from Skill > to Command > : Command >https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/66107/axldesignflip/1408826Thu, 02 Jul 2026 06:37:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ba18769f-eaff-4392-a6b8-d0f7efc925ccDavidAhlI got confirmation from our support that it is a bug in 25.1. They have created a case with Cadence to get it fixed.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66123/disable-cm-updates-or-audits-during-component-replace-through-tcl/1408824Wed, 01 Jul 2026 14:19:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e286fb08-0310-4d59-8264-39d2d0d9e8b7PatEscherI would need to confirm this with our client, but I am pretty sure that Constraint manager is enabled. Cadence Version is SPB 23.1https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66123/disable-cm-updates-or-audits-during-component-replace-through-tcl/1408823Wed, 01 Jul 2026 12:46:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:727cbdef-9344-4b5f-a1b1-3f15b511afb9TechnoBobbyHi PatEscher , Just to narrow this down, these connectivity updates are typically triggered when Constraint Manager is active in Capture. Could you please confirm if Constraint Manager is enabled from Schematic Capture in your setup and whether you are actively using it in this design? Also, it would be helpful to know which Capture version you are currently using. These CM push and ECSet audit messages are generally observed only when Constraint Manager integration is enabled, so this information will help in understanding the behavior more accurately.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66059/standardizing-design-settings-in-orcad-x-capture-cis/1408821Wed, 01 Jul 2026 11:09:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:04b2d93f-f017-4a0b-9550-d13f4894b6fbUlf KIt is the menu box itself I was referring to. When someone wants to place an arbitrary test and want to use eg. Courier, the text box in the add-text-canvas displays (Cadence) proportional text like tms roman, arial etc. This font cannot be changed. It is only possible to see the resulting alignment when having opted for courier only after the text has been placed in the schematic drawing. If the alignment (like having (white) spaces is wrong, the only way to correct it is to edit the text and in that edit box add or remove the (white) spaces.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66123/disable-cm-updates-or-audits-during-component-replace-through-tclWed, 01 Jul 2026 10:08:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a73d5503-cb9e-4206-a2b6-d50e3c3e2177PatEscherHello, we have written TCL code which programmatically replaces a component instance on the schematic with another one from the CIS library. For this we do a full replace, set all the properties and also consider any user properties and merge them. so a quite complex process, but everything is working fine. But we see some performance issues when doing this in OrCAD. Apparently OrCAD tries to update CM connectivity and XNets when we do this. we see in the status bar messages like "Pushing Connectivity changes in CM" , "ECSet Audit on Net Connectivity" Change, etc. is there any possibility to turn these updates off when we do the replace of the instance (it is not a single instance, but can be dozens or hundreds) and then later on turn it on again and do the 'full update' ? Can this be done through a tcl command, maybe like DboDesign_SetConnectivityUpdateTracking or maybe some Preference Settings? Thanks Patrickhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66112/how-can-i-install-16-6-era-allegro-free-physical-viewer/1408820Wed, 01 Jul 2026 07:28:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9dee5b71-3205-41f7-abf8-240083afcf11CT202606302343community.cadence.com/.../db-doctor-23-1-downloadhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66112/how-can-i-install-16-6-era-allegro-free-physical-viewer/1408819Wed, 01 Jul 2026 07:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:5389352b-9b4a-469b-a1a8-ccbc22251ee3CT202606302343FYI. community.cadence.com/.../db-doctor-23-1-downloadhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66059/standardizing-design-settings-in-orcad-x-capture-cis/1408815Wed, 01 Jul 2026 06:13:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:577e4718-3a76-4cdd-9b68-cdd75ebbd6feJeetUlf, Currently these are the available fonts in Place > Text as shown below- As per your suggestion Cadence should add a feature by which designers can add a Text apart from a single word correct or you are looking for a particular font named Andale Mono ? Let me know if I am missing anything.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66115/fanout-of-outer-layer-gnd-smd-pins-to-via-in-pad-in-allegro/1408814Wed, 01 Jul 2026 05:22:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ae1020f4-770f-43d0-bfbb-e3a1e838161aexcellon1Hi There is no fully automated batch-driven flow that I am aware of for this operation like a one click button, however it can be done fairly easily. The key to this operation is basically selecting the items you need. Normally the fanout operation is based on the component pin and it can do a very nice job in this regard. Since you want specific nets only and the associated pins & are also looking to do the whole board you basically need a query that will sort out what you need. Allegro/Orcad has great flexibility in this regard. It can even do specific padstacks only globally across the board in one go if needed. Anyway, look at "Find by Query" to select the items you want first. When you run the query you should see the items you choose highlight on the board. Then invoke the fanout and choose via in pad with your custom padstack to seed the padstacks. Its also possible to save the query so you can run it later or modify it to another task. Best regards.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66110/when-creating-a-new-blank-project-in-syscap-the-default-parameter-settings-for-the-electrical-grid-and-display-electrical-grid-within-the-software-s-grid-options-are-unreasonable/1408813Tue, 30 Jun 2026 16:36:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8d9cce1f-f258-48dc-8bb8-b4d2715149bcZhifeng JinHi rg13, your reply addresses the site-level global configurations deployed in large enterprises. The usage scenario I am reporting here involves no site-level configurations enabled, with only user-level configurations in effect. In this case, all grid parameters are fully controlled via the grid settings within the software UI. This is why I argue that the original default values for Electrical Grid and Display Grid are poorly configured.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66119/leveraging-design-review-markups-in-orcad-x-capture-cis-25-1Tue, 30 Jun 2026 14:10:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d43ac01e-d822-4ed9-8016-e39fa82255b5MohitSCollaboration plays a critical role in today’s schematic design workflows, especially when multiple engineers are working on the same project. Traditional feedback methods—like emails or screenshots—can often lead to miscommunication and delays. To address this, OrCAD X Capture CIS 25.1 introduces the Design Review and Markup feature, enabling a more streamlined and interactive review process directly within the schematic environment. What is Design Review & Markup? The Design Review and Markup feature allows users to: Add comments directly on the schematic canvas Highlight areas using graphical markups (rectangles and arrows) Tag team members for collaboration Embed review feedback within the design itself This ensures that all stakeholders can view and act on feedback within the same design. Add Comments & Markup Open your schematic in OrCAD X Capture CIS Go to Tools → Markup (opens Comments panel) Click New Comment Mark the area using: Rectangle ➝ highlight region Arrow ➝ point to object Enter your comment (use @username to tag users) Click Submit → Comment is saved in design Review & Respond to Comments Open schematic and go to Tools → Markup Select a comment → Auto-zoom to location Add replies or update feedback Mark as Resolved once addressed The Design Review and Markup feature in OrCAD X Capture CIS 25.1 brings collaboration directly into the schematic, enabling teams to communicate more efficiently and reduce design iteration cycles.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66110/when-creating-a-new-blank-project-in-syscap-the-default-parameter-settings-for-the-electrical-grid-and-display-electrical-grid-within-the-software-s-grid-options-are-unreasonable/1408811Tue, 30 Jun 2026 11:10:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:60005979-b1f1-4cb1-9d8c-e829831d82ferg13Thanks for sharing all your observations! Whatever grid unit is set at site level, it will take that into consideration and will not allow user to change the unit from inside the tool.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66117/join-us-for-a-lunch-learn-session-on-allegro-x-system-capture-on-july-9th-at-cadence-bangaloreTue, 30 Jun 2026 09:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7d1f8b93-378b-46d7-980b-48ec1417daa3Renu VibhaYou are cordially invited to an exclusive Lunch & Learn session on Allegro X System Capture – the next-generation schematic technology built to accelerate your design productivity. Discover how System Capture helps your team design faster, smarter, and right-first-time through powerful automation and built-in intelligence. Session Agenda: One-Stop Library Cockpit – Unified Search & Part Manager for instant component access Core Capabilities – Version Control, Variant Editor, and 120+ built-in Audit Checks Productivity Boosters – Decap Wizard and TCL Script Automation for rapid design cycles Integrated Layout Experience – Cross-probe, floorplan edits, and full-fledged Constraint Manager Join us at the Cadence Bengaluru Office for an interactive session and networking with our experts — over lunch. Session Speakers: Shikhar Dwivedi - Principal Application Engineer Bhargava Hegde - Senior Application Engineer Event Details Date: Thursday, 9 July 2026 Time: 10:00 AM – 2:00 PM IST Venue: Agamya Training Room, 1st Floor, Campus 4A & 4B, RMZ Ecoworld, ORR Road, Bengaluru Seats are limited. Please confirm your participation ASAP by writing to hbhargav@cadence.com or dshikhar@cadence.com We look forward to hosting you!https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66115/fanout-of-outer-layer-gnd-smd-pins-to-via-in-pad-in-allegroTue, 30 Jun 2026 05:28:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b1e44c77-a298-4597-8462-c0f5c67265d7BC202603263145I am looking for a solution to select all GND smd pins on the outer layers (TOP/BOTTOM) and fan them out directly to a custom via-in-pad (user-defined padstack) using a fully automated, batch-driven flow. Is there any set of steps that I could try?filterfanoutAllegro PCB Editorhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66097/how-do-i-cut-only-a-cline-segment/1408808Tue, 30 Jun 2026 05:17:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:43ab546f-3c65-4715-96db-e910fda42aaaBC202603263145Thanks! JuanCRhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66112/how-can-i-install-16-6-era-allegro-free-physical-viewerMon, 29 Jun 2026 14:18:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0a77230a-eeba-4ea9-b0ef-9ead19f10d82CF20260629245Hi there, I'm looking to install an older version of the Allegro Free viewer to see an older pcb. How can i do this?Allegro PCB EditorAllegro