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<?xml-stylesheet type="text/xsl" href="https://community.cadence.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>PCB Design &amp; IC Packaging (Allegro X)</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/</link><description /><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><item><title>Forum Post: Quick Tip: Streamlining Continuity &amp; Test Routing with the Daisy Chain Generator in Allegro X Advanced Package Designer (APD)</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-apd/74775/quick-tip-streamlining-continuity-test-routing-with-the-daisy-chain-generator-in-allegro-x-advanced-package-designer-apd</link><pubDate>Fri, 06 Nov 2026 15:46:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b152f112-c0fd-4d5c-9c17-f8a32c3b1dd4</guid><dc:creator>Gowtham P</dc:creator><description>Creating daisy-chain structures manually for package test vehicles and reliability testing can be time-consuming. The Daisy Chain Generator in Allegro X APD simplifies this by helping create and validate daisy-chain connectivity between the package and die or board , making it easier to check connections and isolate potential failures. Why is it useful? Multiple path options: Horizontal S, Vertical S, Angle S, Coil, Custom, Scribble, Snake, and imported geometry such as DXF/GDS. Flexible connectivity: Configure different numbers of pins on the substrate and complementary die/board sides. Routing automation: Create clines and optionally add vias/structures for internal-layer routing. Test-point support: Add and customize test points to provide access to individual chain segments and help isolate open connections. Connectivity verification: Export substrate and complementary-side netlists and display complementary links for visual verification. How to Get Started Go to Route &amp;gt; Daisy Chain Generator in Allegro X APD Select the pins and choose a path pattern such as Horizontal S, Coil, Scribble, or Snake . Configure the substrate and complementary-side connections. Define routing, vias/structures, net names, and test points as needed. Generate the chain and visually verify the connectivity. Have you used the Daisy Chain Generator in your package designs? What has your experience been?</description><category domain="https://community.cadence.com/cadence_technology_forums/pcb-design/tags/daisy%2bchain%2bgenerator">daisy chain generator</category><category domain="https://community.cadence.com/cadence_technology_forums/pcb-design/tags/APD">APD</category></item><item><title>Forum Post: RE: Using Capture CIS 25.1 using ORCAD X professional plus and my license is active and cloud access is on, but I am told I am Offline and when trying to use parts from the library I get an error message.</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/74746/using-capture-cis-25-1-using-orcad-x-professional-plus-and-my-license-is-active-and-cloud-access-is-on-but-i-am-told-i-am-offline-and-when-trying-to-use-parts-from-the-library-i-get-an-error-message/1435025</link><pubDate>Fri, 06 Nov 2026 09:21:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d447cfd0-0622-4c69-9fe8-965a99dea8b5</guid><dc:creator>maxx1234</dc:creator><description>Has it been fixed yet ? I am still having the same issue.</description></item><item><title>Forum Post: RE: PSpice for TI Installation Fails - HTTP 403 Forbidden</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/74748/pspice-for-ti-installation-fails---http-403-forbidden/1435024</link><pubDate>Fri, 06 Nov 2026 07:26:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:173e733e-1a87-49c7-aa29-5dbc93b3de7e</guid><dc:creator>ZD202611052735</dc:creator><description>I have exactly the same issue. Can you please support !</description></item><item><title>Forum Post: RE: PACK_SHORT Property on Heterogeneous Symbol Causes Error</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/59144/pack_short-property-on-heterogeneous-symbol-causes-error/1435023</link><pubDate>Fri, 06 Nov 2026 07:18:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e59ed093-f959-41f2-9b57-73496de45fef</guid><dc:creator>tzsolt</dc:creator><description>In the olb library if I delete from the other sections only the value of the PACK_SHORT property then the value disappear from the original section too!</description></item><item><title>Forum Post: RE: Looking for a transition zone for Rigid Flex .</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/74767/looking-for-a-transition-zone-for-rigid-flex/1435020</link><pubDate>Thu, 05 Nov 2026 18:16:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d07d8fed-76ec-46c3-8d1d-0d1b8b38edf2</guid><dc:creator>Mhawley1</dc:creator><description>hello , thank you for this . We can give a try at skill code , , I guess sampling the vector of the Clines and seeing that they are normal to the some unique class line at the boundary . Ill talk with the group at the company and if we device some solution ill post it here.</description></item><item><title>Forum Post: RE: Looking for a transition zone for Rigid Flex .</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/74767/looking-for-a-transition-zone-for-rigid-flex/1435019</link><pubDate>Thu, 05 Nov 2026 15:28:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b155bf11-856d-4937-8202-71406337c160</guid><dc:creator>JuanCR</dc:creator><description>Hi Mhawley1 . I&amp;#39;ve looked into our database and it doesn&amp;#39;t seem like there&amp;#39;s a DRC that would check this. If enforcing perpendicular trace routing across zone/bend boundaries is required for manufacturing or rigid-flex design guidelines, this can be achieved using Allegro Relational Rule Developer (Ravel) or custom SKILL scripts.</description></item><item><title>Forum Post: PSPICE for TI installation</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/74771/pspice-for-ti-installation</link><pubDate>Wed, 04 Nov 2026 10:58:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b69b219a-e266-4ae7-92ea-8973f1b0f9fc</guid><dc:creator>FT202611041530</dc:creator><description>Hello, Issue when installing &amp;quot;PSPICE for TI&amp;quot;, I saw some posts on the same subject, is cadence working to resolve ? The snapshot of the error and the log are attached below community.cadence.com/.../cdsPSpiceNetworkStatus.txt community.cadence.com/.../cdsPspiceTIlog.txt</description></item><item><title>Forum Post: How to turn off Internet databases (Samacsys, et al.)</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/74770/how-to-turn-off-internet-databases-samacsys-et-al</link><pubDate>Wed, 04 Nov 2026 09:28:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1aaae313-29c3-413b-bc9d-c488a8d2d4ca</guid><dc:creator>Ulf K</dc:creator><description>Forum Experts, Is there a way to turn off/disable the Internet based component database options in Component Explorer (like Samacsys et al.) ? I only use the built in CIS option with a local database which I maintain myself. My customers provides me with component info (schematics and footprints). I get them either by mail or create them myself using the standards/rules that my customers have defined. Have been looking where the capture.ini files and other reside but have found no configuration entries (that I dare experimenting with).</description></item><item><title>Forum Post: RE: Capture CIS 403 Error</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/74765/capture-cis-403-error/1435015</link><pubDate>Tue, 03 Nov 2026 16:02:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:08a77582-f15e-45ee-8a57-34067134fd51</guid><dc:creator>CP202609102340</dc:creator><description>This was stated to be resolved by the end of the last week. It is server side on Cadence&amp;#39;s end. It is still being worked on. I&amp;#39;ve tried much of the same as stated under my post.</description></item><item><title>Forum Post: Looking for a transition zone for Rigid Flex .</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/74767/looking-for-a-transition-zone-for-rigid-flex</link><pubDate>Tue, 03 Nov 2026 12:58:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:4d87b49a-0e21-45d5-be57-649eb8b9f184</guid><dc:creator>Mhawley1</dc:creator><description>Hey Everyone I got a quick question , Is there a constraint region for Flex designs that forces the traces to be normal to the edge of the board ? Ya know so the traces are straight going in and out of the flex zone ?</description><category domain="https://community.cadence.com/cadence_technology_forums/pcb-design/tags/flex%2bpcb">flex pcb</category></item><item><title>Forum Post: RE: Footprint viewer in Capture CIS 26.1 fails to display.</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/74763/footprint-viewer-in-capture-cis-26-1-fails-to-display/1435012</link><pubDate>Mon, 02 Nov 2026 19:36:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d0a3f83a-014c-440c-a85e-77ffa1b869ed</guid><dc:creator>Ulf K</dc:creator><description>Thanks - If there was only a way to make dBDoctor_ui.exe do its work in a &amp;quot;quiet&amp;quot; mode. For each file, dBDoctor_ui opens a command window, that starts with @echo off, does what it is supposed to do and then closes that window. IMHO, maybe Cadence should add a check box &amp;quot;Use Quiet mode and display a % iprogress indicator only [x]</description></item><item><title>Forum Post: Capture CIS 403 Error</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/74765/capture-cis-403-error</link><pubDate>Mon, 02 Nov 2026 19:23:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:17d75675-3dfe-428a-9b1b-1c038e1eca35</guid><dc:creator>TC20260902865</dc:creator><description>I have been receiving the attached error for about 2 weeks now and can not seem to find a resolution. I have tried reinstalling the software, but it has not fixed the issue. My device is online and other apps are working normally. The error is only in Capture CIS, Presto works just fine.</description><category domain="https://community.cadence.com/cadence_technology_forums/pcb-design/tags/OrCAD%2bX%2bCapture%2b25-1">OrCAD X Capture 25.1</category></item><item><title>Forum Post: RE: Footprint viewer in Capture CIS 26.1 fails to display.</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/74763/footprint-viewer-in-capture-cis-26-1-fails-to-display/1435009</link><pubDate>Mon, 02 Nov 2026 15:05:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a37bb170-6d2d-4f3c-9589-e2470a23ce64</guid><dc:creator>oldmouldy</dc:creator><description>This does work fine if the Symbol files, DRA, ?SM and PAD, are up to date. The installation of my colleague is working with files processed with DB Doctor 24.1, my installation is working with files processed with DB Doctor 26.1. Both CIS Explorer and Show Footprint are correct.</description></item><item><title>Forum Post: Footprint viewer in Capture CIS 26.1 fails to display.</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/74763/footprint-viewer-in-capture-cis-26-1-fails-to-display</link><pubDate>Mon, 02 Nov 2026 13:03:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8aa5235c-3dbb-4c63-8d83-0d8f2f5eacbf</guid><dc:creator>Ulf K</dc:creator><description>Using W11 26H2 Professional. Capture CIS 26.1 - Footprints not visible in either place part (CIS explorer) or place component (manually) This sort of bug has been reported and corrected in a Hotfix for previous versions that had the same problem but the missing footprint view problem has popped up again. When using CIS explorer and selecting a a component for which a footprint is defined, the &amp;quot;bar&amp;quot; lits up in green but only the schematic symbol appears in the upper right corner. The layout symbol preview does not. This works in 25.1 but not in 26.1 Using the same database configuration (.DBC) file. I have 25.1 and 26.1 installed on my computer. All DIR0, DIR1 etc. settings are identical. Settings in capture.ini is the same according to below: community.cadence.com/.../orcad-tip-of-the-week-footprint-viewer-in-orcad-capture Are there any new added configuration settings that needs to be configured?</description></item><item><title>Forum Post: It Worked the First Time! Why Does My SKILL Code Fail on the Second Run?</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/74760/it-worked-the-first-time-why-does-my-skill-code-fail-on-the-second-run</link><pubDate>Sat, 31 Oct 2026 14:35:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:af85a1d9-ef55-4c28-9401-1e0876dd4a91</guid><dc:creator>JuanCR</dc:creator><description>Have you ever run a SKILL function successfully, only to find that running it again produces an error or unexpected behaviour? One common cause is that the first execution changes the database or application state that the code assumes will still be available on the next run. For example, your code may keep references to database objects that have since been deleted, replaced, or modified. A useful troubleshooting technique is to avoid relying on database object IDs stored globally between executions. Instead, retrieve the objects you need each time the function runs and validate the returned values before operating on them. For instance: procedure(processSelectedObject() let((obj) obj = car(axlGetSelSet()) if(obj then printf(&amp;quot;Current object: %L\n&amp;quot; obj) ; Process obj here else printf(&amp;quot;No object is currently selected.\n&amp;quot;) ) ) ) This also demonstrates another useful habit: check the result before using it . For example: obj = car(axlGetSelSet()) when(obj printf(&amp;quot;Selected object type: %L\n&amp;quot; obj-&amp;gt;objType) ) Database objects aren&amp;#39;t the only thing to consider. A SKILL script can also change session state such as the current selection or Find Filter. If your function depends on a particular state, the second execution may start under different conditions than the first. When debugging this kind of problem, try this approach: Run the function once. Check what changed in the design or session. Run it again and identify the first operation that behaves differently. Add printf() statements around your operations. Inspect database objects and return values instead of assuming they are valid. Where appropriate, reacquire database objects rather than relying on references retained from an earlier execution. These steps are crucial specially when you&amp;#39;re testing loose SKILL commands, where moving the canvas, zooming in or modifying the position of the elements might change the dbIDs of the objects. The important question isn&amp;#39;t always &amp;quot;Why did my SKILL code fail?&amp;quot; Sometimes the better question is: &amp;quot;What did the first execution change that the second execution wasn&amp;#39;t expecting?&amp;quot; That small shift in troubleshooting approach can make intermittent SKILL problems much easier to isolate. Have you encountered a SKILL function that behaves differently on its second execution? What was the root cause, and how did you track it down?</description><category domain="https://community.cadence.com/cadence_technology_forums/pcb-design/tags/Skill%2bprogramming">Skill programming</category><category domain="https://community.cadence.com/cadence_technology_forums/pcb-design/tags/debugging">debugging</category></item><item><title>Forum Post: RE: Associate psice model greyed out</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/66186/associate-psice-model-greyed-out/1435002</link><pubDate>Fri, 30 Oct 2026 13:42:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:62404f59-28d4-40c7-bebf-b043aeb21e0c</guid><dc:creator>IshaS</dc:creator><description>Hi Shashank, Are those PSpice components?</description></item><item><title>Forum Post: RE: Electrothermal model in MbreakN or other mosfet models?</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/74730/electrothermal-model-in-mbreakn-or-other-mosfet-models/1435001</link><pubDate>Fri, 30 Oct 2026 13:40:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0f302851-489c-476c-bed9-31a9e5faf9f4</guid><dc:creator>IshaS</dc:creator><description>Hi US202607259240 , Which MOSFET parameters do you specifically need to vary with junction temperature, for example RDS(on), threshold voltage, mobility/transconductance, leakage, or capacitances? Could you share the PSpice version you are using?</description></item><item><title>Forum Post: RE: PSpice for TI installer fails: HTTP 403 Forbidden downloading TI_URLs.txt</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/74751/pspice-for-ti-installer-fails-http-403-forbidden-downloading-ti_urls-txt/1435000</link><pubDate>Fri, 30 Oct 2026 13:35:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:933ab38c-17d7-4745-abf3-956dd57481e3</guid><dc:creator>IshaS</dc:creator><description>Hi ZS202610299347 , Can you please share the snapshot of the error message received. Are you getting some installer output, can you please share it.</description></item><item><title>Forum Post: RE: PSpice for TI Installation Fails - HTTP 403 Forbidden</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/74748/pspice-for-ti-installation-fails---http-403-forbidden/1434990</link><pubDate>Fri, 30 Oct 2026 02:23:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a7d1a218-7acb-4969-8f29-b075a383f2a3</guid><dc:creator>BD202610298111</dc:creator><description>I can confirm the same PSpice for TI installation issue on October 30, 2026. TIPSpice.exe fails while downloading TI_URLs.txt from pcb.cadence.com with HTTP 403 Forbidden. The issue is reproducible across multiple installation attempts. Could Cadence confirm whether the download endpoint is currently unavailable and provide a supported workaround?</description></item><item><title>Forum Post: RE: Using Capture CIS 25.1 using ORCAD X professional plus and my license is active and cloud access is on, but I am told I am Offline and when trying to use parts from the library I get an error message.</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/74746/using-capture-cis-25-1-using-orcad-x-professional-plus-and-my-license-is-active-and-cloud-access-is-on-but-i-am-told-i-am-offline-and-when-trying-to-use-parts-from-the-library-i-get-an-error-message/1434989</link><pubDate>Thu, 29 Oct 2026 20:12:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6b0221ae-2465-4aa8-8edd-874ae5ed4494</guid><dc:creator>CP202609102340</dc:creator><description>No unfortunately I have not. I believe it is a server side issue on Cadence&amp;#39;s end as I seem to have exhausted all other measures. I have spoken with quite a few others as well who are having similar issues. Notably similar problems from other recent posts might indicate that within the week it will be remedied.</description></item></channel></rss>