https://community.cadence.com/cadence_technology_forums/pcb-design/en-USTelligent Community 13https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/66340/extract-areas-on-the-fpcb-that-do-not-contain-arcs/1421090Fri, 25 Sep 2026 13:13:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:287d9cb4-c88f-470d-9eaf-4fee214dfdfbSG20260713408Thanks, Hoangkhoipcb! I appreciate you sharing such concise code. I’m still studying to fully understand it, but I’ll take your code to heart; it will certainly help me think about writing code more concisely or elegantly. I’d love to ask for your email address, but given the nature of this community, I feel it’s not the right place for private conversations. I may lack expertise myself, but I notice that high-level script developers aren't providing answers here. Here are my personal thoughts on the code: 1. I’m not sure why the "prog" function was used. 2. There is no exception handling. - If a cline segment (or cline) is connected to a via, pin, or shape, there is no need to extract the point. 3. The order of the results was determined for the sake of the next step. - The angle of the result doesn't matter; the designer just needs to be able to verify the result. (Though it would be useful for debugging purposes.) - If layers are mixed, unnecessary screen control operations are repeated. 4. When I was a beginner, I used to put every function into a single block, but as the code grew longer, it became difficult to review or maintain, so I separated the log file generation. Ultimately, I decided to create separate functions for each specific task. thank you~~https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/70337/how-to-set-the-voltage-value-and-type-within-start_reliability-in-site-cpmFri, 25 Sep 2026 09:14:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9d909006-91a4-4413-83f6-c9bafe05003fMZ20250602835Dear all, i use currently System Capture Version 25.1 S050. May i ask if it is possibile to set the voltage value and type within START_RELIABILITY in site.cpm file? START_RELIABILITY POWER_NETS '1V8D' '3V3' '3V3D' 'VIN_D_PCB1' '2V2' END_RELIABILITY Many thanks and best Regards Moyanhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/66340/extract-areas-on-the-fpcb-that-do-not-contain-arcs/1421089Fri, 25 Sep 2026 04:36:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:04d4adb5-edc2-47fd-8849-f75b16d4b4f1HoangkhoipcbHi SG20260713408 , I tested your code, and it works well for me. I've made a shorter version of the code for you to reference. axlCmdRegister ( "create_arc_chk" 'create_arc_chk ) ( defun create_arc_chk ( ) ( let () prog (() axlSetFindFilter (?enabled '( "noall" "CLINES" ) ?onButtons '( "all" )) while ( axlSelect () clines = axlGetSelSet () axlClearSelSet () tmp_list = nil seg_list = nil Out_file = outfile ( "create_arc_chk.log" "w" ) fprintf (Out_file "%-5s %-7s %-10s %s \n " "No" "Angle" "Layer" "Location" ) foreach (cline clines segs = cline-> segments foreach (seg segs if ( length ( member (seg segs)) > 1 then next_seg = cadr ( member (seg segs)) if (seg-> xy == nil && next_seg-> xy == nil then ol = axl_ol_ol2 (seg-> startEnd next_seg-> startEnd ) if ( member ( car (ol) tmp_list) == nil then angle = abs ( axlRadToDeg ( axlGeoAngleBetweenLines( seg-> startEnd next_seg-> startEnd ))) if ( axlGeoEqual (angle 0.0 ) || axlGeoEqual (angle 180.0 ) then else push ( car (ol) tmp_list) fprintf (Out_file "%-5d %-7.2f %-10s %L \n " length (tmp_list) angle cadr ( parseString (seg-> layer "/" )) car (ol) ) push (seg seg_list) push (next_seg seg_list) ) ) ) ) ) ) close (Out_file) if ( length (tmp_list) > 0 then axlHighlightObject (seg_list) axlUIViewFileCreate ( "create_arc_chk.log" "Arc Segments Check" nil ) printf ( "Errors : %d \n " length (tmp_list)) ) ) ) ) ) BR, HoangKhoihttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/65000/trimming-a-shape-corner/1409380Wed, 23 Sep 2026 19:49:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ec5f1fc3-cec7-4691-be5c-11212d39a217BM202507107724Thanks FaPb!!! This is the critical step. This will not work without "Other segs" selected. Having just "Shapes" selected will not invoke the small cross when hovering.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66323/join-our-next-live-ask-me-anything-session-on-system-capture-on-september-23-2026/1409378Wed, 23 Sep 2026 16:06:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:56af3231-112e-4309-827d-b2b8aefc7c93AyushDThank you for the great questions and engagement today. Feel free to add questions if you have any..https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66323/join-our-next-live-ask-me-anything-session-on-system-capture-on-september-23-2026/1409377Wed, 23 Sep 2026 16:03:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f12fbdde-8b7f-47d4-b9fd-11fc8ceb0ab2EDAHutthanks. Will try this. We do get impacted by duplicated schematics at timeshttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66323/join-our-next-live-ask-me-anything-session-on-system-capture-on-september-23-2026/1409376Wed, 23 Sep 2026 16:03:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1da0ba4a-3d36-41f2-aaea-e95d2b079d68AyushDwhen you are working on a shared design, whenever you open any project from pulse you acquire a lock on that design and other users with whom the design is shared they will see a lock icon on the design as it is being worked upon by another user and once 1st user is done with the changes and commits the design, the lock will be removed for other user to modify the design. Similarly if it is page level sharing, users will see the lock on particular page that is being worked upon by other user. If you commit your changes to the design efficiently it should avoid any conflicts.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66323/join-our-next-live-ask-me-anything-session-on-system-capture-on-september-23-2026/1409375Wed, 23 Sep 2026 15:57:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d26a27ef-e4df-4589-9ed7-d232faa2fb78JasmineHi, In Allegro X System Capture, the preferred workflow for managing hierarchical blocks when underlying schematics vary slightly across product variants relies on Variant Management. This avoids maintaining separate, duplicate schematics and preserves the integrity of design reuse.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66323/join-our-next-live-ask-me-anything-session-on-system-capture-on-september-23-2026/1409374Wed, 23 Sep 2026 15:56:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:4aa82e52-b941-499a-89c6-c91b972789bcEDAHutAlso, for teams working simultaneously on the same system design, what can be the best practices for avoiding database conflicts during real time co-design ?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66351/is-there-a-way-to-replace-cache-for-all-components-at-once/1409373Wed, 23 Sep 2026 15:55:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:70950cd6-a9c9-44a6-adba-8a90221e0ea0rg13In Orcad Capture, Replace path in design cache utility can be used to replace design cache path. Please find following link of article which talks about the same: Article (20159217) Title: How to use ‘Replace path in design cache’ option given in Allegro Design Entry CIS? URL: https://ask.cadence.com/ASK/article-viewer?id=a1Od0000000swShEAI&pageName=article-viewer See if it fulfills your purpose.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66323/join-our-next-live-ask-me-anything-session-on-system-capture-on-september-23-2026/1409372Wed, 23 Sep 2026 15:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:757687cb-68a9-473e-9297-945405f7b2c5EDAHutHello Experts Could you advise on the preferred workflow for managing hierarchical blocks when the underlying schematic needs to vary slightly between different product variants ?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66351/is-there-a-way-to-replace-cache-for-all-components-at-onceWed, 23 Sep 2026 15:49:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:10df0f58-dd03-4a68-b665-c83a4ffd5800LogicNetHi all, When sharing a design with another engineer, I understand that if the schematic libraries are located in a different location, the recipient can use Replace Cache from the Design Cache to synchronize the design with the new library location. This works well for a small number of parts, but on larger projects containing hundreds of components, updating the cache one part at a time can become very time-consuming. Is there a method in OrCAD Capture to automatically update or refresh all cached parts in a design against the referenced libraries in a single operation? Thanks!Capture CIShttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66323/join-our-next-live-ask-me-anything-session-on-system-capture-on-september-23-2026/1409371Wed, 23 Sep 2026 15:03:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0d7af3c6-232d-4e86-adb4-7af1e2907420AyushDWelcome everyone to the session !! Feel free to post your queries here ..https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66350/markups/1409370Wed, 23 Sep 2026 12:59:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:5743c15a-7c70-40ff-bb3f-5ec8e7a2f3cfBenniginI opened the example design "Cadence_Demo.brd" and got the same result in both versions 24.1 and 25.1. Also, happens with all my designs.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66350/markups/1409369Wed, 23 Sep 2026 12:52:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0536df55-fcae-4f17-aa26-97038e21c88dJeetCould you check whether this issue is specific to a particular board or occurs with all board designs? Please test with a board file available at C:\Cadence\SPB_25.1\share\pcb\examples\board_design and let us know whether you encounter the crash.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66350/markupsWed, 23 Sep 2026 12:33:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8121b191-2795-43ad-b4e4-5fc613189343BenniginWhen trying to add a Markup to my design, PCB editor crashes when I click submit. Anyone else seen this issue and found the solution? I have tried it using version 24.1-2024-S010 and 25.1-2025-S050. Thanksmarkuphttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66346/how-do-we-create-borders-in-system-capture-or-add-our-company-logo-and-other-custom-variables/1409367Wed, 23 Sep 2026 09:17:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:66bf06a9-4c91-4482-9445-7fbf03a468c4steveThis should help How to create or customize page borders in Allegro X System Capturehttps://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/66336/error-orcommn-2302-cannot-initialize-profile/1409366Wed, 23 Sep 2026 06:58:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c11fc625-9266-4e6b-a8a5-e665f1949609VolkerDHi Isha, thanks for your answer. Just to make sure what you want be to try... This is the structure in my registry: \CaptureWorkSpaceEx\24.1.0\BCGWorkspace \CaptureWorkSpaceEx\ 24.1.0\D:\PSPICE_WORKING_DIR\cdssetup\OrCAD_Capture/24.1.0/capture.ini\ \CaptureWorkSpaceEx\25.1.0\BCGWorkspace (no subfolder "\PSPICE_WORKING_DIR" here) Should I delete the hole folder \CaptureWorkSpaceEx with all subfolders? Or only the subfolder \25.1.0? Or something else? 24.1 is working fine, the problem only occurs for 25.1. The subfolders to PSPICE_WORKING_DIR are missing there. Thanks in advance and best regards!https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/66336/error-orcommn-2302-cannot-initialize-profile/1409365Wed, 23 Sep 2026 05:41:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:34456b8f-da78-4f4a-8c2a-0562f3f29817IshaSHi Volker, Can you please try below: Select File > Exit to close Capture and PSpice application (if running). Go to Windows Task Manager and c lose all cadence running tools. Now, Delete the Capture workspacex registry from registry editor: HKEY_CURRENT_USER\Software\OrCAD\CaptureWorkSpaceEx Now, invoke PSpice standalone by selecting PSpice AD in Start menu. Now start OrCAD Capture CIS, open the design, and check the problem. Try this and let me know how it goes!!https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66349/using-advanced-find-operations-and-efficiently-search-for-objects-in-orcad-x-capture-cisTue, 22 Sep 2026 14:38:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e850bede-0184-4a54-8b70-d210e3d5c4f7MohitSIn a schematic design, locating specific components and identifying properties across multiple objects can be challenging, especially in large designs. Starting with OrCAD X Capture CIS 25.1, the Find and Replace feature has been enhanced to support advanced search operations, allowing you to locate schematic objects using property-based filters and display attributes. 1. Open your schematic design in OrCAD X Capture CIS 25.1 . 2. Choose Edit > Replace . 3. Select the required object type (Parts, Pins, H-Pins, and so on). 4.Enter a search pattern (for example, R * to find all resistors) and click Find . The matching objects are displayed in the Find Results window, enabling quick navigation to the selected objects. 1. To further refine the search, click the + icon in the Find Properties section and add a new property criterion. 2. Select the desired property from the drop-down list. For example, choose Tolerance . 3. Specify the required property value, such as 5% . 4. Click Highlight and then select Find . The search returns all resistors with a Tolerance value of 5% , and the corresponding symbols are highlighted directly in the schematic. The enhanced Find and Replace functionality helps you quickly locate objects, perform property-based searches, validate design data, and efficiently navigate large schematics with greater precision. Have you tried the enhanced Find and Replace feature in OrCAD X Capture CIS 25.1? Share your experience and favorite use cases in the comments below!