https://community.cadence.com/cadence_technology_forums/pcb-design/en-USTelligent Community 12https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66067/orcad-capture-annotation-issues-for-a-heterogenous-part-in-a-hierarchical-designSat, 13 Jun 2026 03:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7138f46e-0d0d-4646-8714-96ee5bef9967SF202503203610I have a hierarchical block that is used 64 times. Within that block I have a quad opamp that was pulled from the included OrCAD library. The reference designators are U?A, U?B, U?C, U?D. When I annotate this block, (Update Selection is selected). I do not get the annotation that I desire. I want Instance 1: U1A, U1B, U1C, U1D Instance 2: U2A, U2B, U2C, U2D .... Instance 64: U64A, U64B, U64C, U64D but what I am getting is Instance 1: U1A, U2B, U2A, U2C Instance 2: U1B, U3A, U2D, U3B etc I have tried using Update Occurrence, Update Instances:, Annotate as per PM Ordering, Annotate as per page ordering in the title blocks, Preserver Designator, and Auto-package Heterogeneous Part Using First Match, and they seem to have no effect. I have tried "Advanced Annotation" but it just opens and locks up. The only button that works is the X to close the window. I even changed the reference designator for this part to UQ?A, UQ?B, UQ?C, UQ?D so that there would be no conflicts with any other "U" parts, and the output was pretty much the same. I have OrCAD X Capture 23.1, but I have noticed this behavior in previous versions of OrCAD. I'm beginning to think the only solution to this is to annotate it, then go in and manually change all 256 reference designators (4x64).https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66059/standardizing-design-settings-in-orcad-x-capture-cis/1408662Fri, 12 Jun 2026 19:28:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2698f6cc-f5ac-463f-988f-7f646a989f6eexcellon1Hi ULF Good idea on the font type. Just a FYI on this. At one time Orcad used to ship their own Orcad font for use in capture. It was in v16.3 or earlier. Perhaps you may have that install somewhere. Anyway, there is a fairly good difference between the number 0 and the letter o. The letter o is like a square with rounded off corners, it is also slightly bigger by a good margin than the number 0. Very easy to see the difference if printed or on the screen. the number 0 looks like () do a search of the cadence folder for *.ttf to see if you have it. On windows I think you can just double click to install it to the Windows\Fonts folder or it could be copied manually too, I cant seem to post a pic of it here, but it does looks nice. Best regards.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66064/debug-the-missing-part-numberFri, 12 Jun 2026 05:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b703de1e-8f65-49da-8bd9-74be396abc29IshaSIn OrCAD X Capture CIS, the Part Number column appears blank in Live BOM and Part Manager for existing components, even though the value exists in the database. The workspace is set to Local . What is the most likely root cause? A. The database is not connected properly, so Live BOM cannot fetch any properties for existing parts. B. In the CIS configuration, the part_number field is mapped to a different OrCAD property name (for example, PART_NUMBER_NEW ) than the property name used by the existing schematic parts. C. Live BOM does not support displaying Part Number information when the workspace is set to Local . D. The existing parts in the design must be re-placed from the CIS database before Live BOM can display the Part Number field. Try the scenario and share observations. Happy Learning !!schematic captureLIVE BOMdesignOrCAD Xhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/1408656Thu, 11 Jun 2026 15:07:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ac89259d-1b6f-4ccf-af05-ef75445dae69JR202606119023Helo mohit ,I am facing that issue in all the board designs .https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/1408655Thu, 11 Jun 2026 15:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3290e07c-11f3-4a7a-a067-a8a559bfca90JR202606119023Hello Mohit, I am using "24.1-2024 S008 [1/12/2026] Windows SPB 64-bit Edition" i am unable to upload a snapshot.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/1408652Thu, 11 Jun 2026 09:28:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:4f1fcde1-f469-4031-befb-97249c60d2e0MohitSHello Thanks for your active participation in the session. I would request you to let your peers know about our interactive and engaging community forum. Apart from capture we have many other product buckets which they can explore to ask any query they have and connect with other designers toohttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/1408651Thu, 11 Jun 2026 09:24:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:bade9f11-b4f3-4cf4-b0bf-6b21fa594dfbMohitSHello, Can you please let me know which version and hotfix you are using. Also can you share a snapshot of the same? Are you facing this issue with a specific board design or the issue is with other designs too?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/1408650Thu, 11 Jun 2026 08:28:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c6d19b59-68f6-4076-9f6a-e973c949d5f0KS202606109251thank you . Yes we have some scenario where we face some issues. I will share.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/1408649Thu, 11 Jun 2026 08:06:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3bce7d2e-b823-49d3-89fa-2abd8930da3fJR202606119023Hello, The top and bottom layers should be external, while other signals should be internal layers. Why isn't this showing up in the Physical constraints, or do I need to enable something in the cross-section?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/1408648Thu, 11 Jun 2026 07:11:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:22e1d2de-1a4c-48de-872f-1b1adb7ee90cJR202606119023Hello, I am using Allegro X PCB Venture in that The top and bottom layers should be external, while other signals should be internal layers. Why isn't this showing up in the Physical constraints, or do I need to enable something in the cross-section? Thankshttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66061/join-us-on-wednesday-june-17-2026-for-a-live-ask-me-anything-dedicated-expert-session-constraint-managerThu, 11 Jun 2026 05:43:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2e758654-195d-4bdf-907e-b287554f56dfRenu VibhaGot Questions on Constraint Manager? Want clarity on new features and solving everyday design challenges? Ask a Cadence expert— LIVE Join Us Here June 17, 2026 | 7:30–8:30 PM IST Topics: Electrical Constraints Physical & Spacing Constraints Let’s make this an engaging, insightful, and impactful session together! Bring your questions. Share your experiences. Be part of the energyhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66060/make-smarter-design-decisions-with-in-design-analysis-leverage-the-upcoming-allegro-x-webinarThu, 11 Jun 2026 05:29:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c4432cc0-50b9-4f16-88a7-90fe2b3fb2ffRenu VibhaStruggling with SI/PI Challenges in PCB Design? Are you looking for clear answers on: How to configure a PCB for in-design analysis using Sigrity X Aurora within the Allegro X environment? How to choose the right layer stack-up for power and ground to minimize PDN inductance? How to validate your routing topology against industry specifications? How to catch and resolve SI/PI issues early—before they become costly problems? If these sound familiar, you’re not alone—these are some of the most pressing challenges faced by PCB designers today. Get the Answers You Need We’ve already covered these exact topics and more in a practical, insight-packed webinar designed for engineers like you. Register Now Why this webinar matters: Step-by-step guidance on real workflows Industry-aligned best practices Actionable techniques you can apply immediatelyhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66033/error-spmhod-i-design-has-been-corrupted-saving-as-autosave-sav/1408645Wed, 10 Jun 2026 16:13:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:86fec4ea-4e87-4b8c-9f15-75d3aba1fc45kevconHi Gowtham, Setting those had no effect, I am still getting the same error. Kevinhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66059/standardizing-design-settings-in-orcad-x-capture-cis/1408643Wed, 10 Jun 2026 15:28:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:245ff557-519d-4246-bcf2-c114c988d55aUlf KThis is a nice feature. May I humbly suggest that Cadence would consider including the font "Andale Mono" (Or Andale dot) in future releases. This font makes it easy to distinguish between captal O and the number 0 as the zero is displayed with a dot in its center. Some versions of zero uses a 0 with a forward slash / in it but that letter is the next to last letter in the Danish alphabet. My 5 eurocents.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/1408642Wed, 10 Jun 2026 15:09:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ab793286-11eb-41b5-8ddb-3a2ddbf59a8aBC202603263145Thanks!https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/1408641Wed, 10 Jun 2026 15:09:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:aebfe098-a57d-493a-bf20-746742d2f39eMohitSThank you everyone for the great questions and engagement today. In case you have additional queries please feel free to post on the respective forums.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/1408640Wed, 10 Jun 2026 15:07:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:36a00e8f-58fc-400c-bbaa-b5fbefb90c42MohitSIn case you are driving constraints from schematic to layout you should define the constraints at early stage of schematic creatin. It is mandatory to have the constraints defined before the netlisting. Constraints can also be defined at PCB editor level and then can be imported back to schematic.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/1408639Wed, 10 Jun 2026 15:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9e046ca2-1524-45e2-b893-9e37edd3bdeeKS202606109251Thank you for the responses…. I am a student… that’s why so many questions …. This was a very good opportunity to interact.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/1408638Wed, 10 Jun 2026 14:56:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1e56a023-8dae-4bcc-b580-6b0cfb84caa4KS202606109251Thank you …. One last question…. How early should we define electrical and physical constraints in OrCad Capture using Constraint Manager?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/1408637Wed, 10 Jun 2026 14:55:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2d6f2833-3741-4f42-a1d0-d0145f62d7a7MohitSHello, There could be many challenges with respect to net connectivity across hierarchical levels. These include port mismatches, global nets issues, missing hierarchical pins. Are there some specific scenarios where you face any difficulty or challenge while working with a hierarchical design?