https://community.cadence.com/cadence_technology_forums/pcb-design/en-USTelligent Community 12https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/66186/associate-psice-model-greyed-out/1408975Thu, 23 Jul 2026 11:24:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ac965806-8a47-48f9-aab6-2bc65ebbd18fShashankHi Isha, Thanks for the reply! In custom libraries(manually created) and online downloaded libraries this option is greyed out. Is there any way to change this to PSpice specific project?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66195/what-is-the-best-way-to-perform-final-review-of-pcbs-if-ai-driven-designs-are-comingThu, 23 Jul 2026 11:21:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:cd39154d-75ea-4f69-94c9-56b0bab554d7John TAI assisted designs are definitely coming. So we can expect to spend a lot more time reviewing designs due to higher/faster output. Should we use AI to review AI driven designs? Or must a human have the final say? So what tools or procedures are you currently following for design review: An independent engineer reviews the board using the .brd file in PCB Editor? An external format is exported for independent review using a Freeviewer or CAD viewer; manual notes sent back to the designer? An external format is exported for review using a specific design review tool? Design is self-reviewed using PCB Editor alone; failures are fully controlled using Constraint Management. Other? You can simply answer by entering a number option from the above or include any reasoning for your answer if you prefer. Alternatives for discussion and opinions are very welcome!quizhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/66186/associate-psice-model-greyed-out/1408974Thu, 23 Jul 2026 11:07:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6ef35d87-9bb8-4aac-998d-e566ed7246acIshaSHi Shashank, This appears to be expected behavior. When a project is created without selecting "Enable PSpice Simulation", the project is treated as a standard schematic project and certain PSpice-specific commands are disabled. One of those commands seems to be Associate PSpice Model. Even though Capture may still allow creation of a Simulation Profile later, the project itself was not initialized with the full PSpice simulation configuration, so some simulation-related UI options remain unavailable. which components do you see as disabled?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66192/constraint-setup-via-tcl-in-asc/1408972Thu, 23 Jul 2026 05:41:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1b5be4d9-394e-4981-8422-25e19a2ba598GelzoneThe English ver: Applications of Electrical Constraint Sets for the first section; Automatic Topology and Updates for the first selection; Creating XNet and Differential Pairs Using the DML Model (same with SPB 16.6) for the second selectionhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66192/constraint-setup-via-tcl-in-ascThu, 23 Jul 2026 05:36:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:77ff1d91-1259-4a5e-9288-9f20f8d53071GelzoneI need to do a manual process for each schematic: Electrical Analysis -> Constraint Manager -> Edit -> a window popup (the screenshot) -> Tools -> Options and check the items below: I found it is not a global setting so I need to set this one by one. I'd like to know is there any command/script can handle this? I just find cnsmgr to open the window but can not manipulate the choice. Or another way, if ASC has a config file just like OrCAD's Capture.ini ? Maybe I can set them in this kind of file.System Capturetclhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66182/cannot-generate-odb-output-for-a-particular-design/1408969Wed, 22 Jul 2026 20:27:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0454a205-d2ac-4959-a787-2058410d5d30Ulf KLast time I saw something about not being able to generate ODB++ was when it was known that the CAD data texts contained truetype fonts.. The Truetype feature was introduced in the PCB Editor version 25.1 (If I can recall) There is a bug in that it is not possible to selct the old type of fonts. The drop-down menu does not work. Instead, the user has to type in the menu text style selection manually, including spaces. A bug report has been filed (by me) but not fixed by cadence so far.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/66189/how-to-use-skill-code-to-check-pin-to-pin-mark-air-gap/1408968Wed, 22 Jul 2026 19:45:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:63e12ecf-485f-486a-a003-8b1ca67f4a5beDaveI'm guessing you are new to Skill? Start by doing a short course to learn Skill basics. (Search ASK for Allegro X PCB Editor SKILL Programming Language Training) Next use ASK to see the syntax of the axlAirGap command and start writing code!https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66190/what-s-your-fastest-way-to-unfix-fixed-objects-in-allegro-pcb-editor/1408966Wed, 22 Jul 2026 15:20:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3790ab6d-1c97-4e55-99c6-99c1e1e24864steveInvoke the Unfix command and right click - Unfix All.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66168/from-challenges-to-solution-interactive-3dx-canvas-session---join-us-on-july-22nd/1408965Wed, 22 Jul 2026 15:06:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9ca7e1f5-b7ee-4e7e-96a3-77111b526a41vidhyaparameswariThe imported STEP model is treated as a mechanical body . While it can be associated with a net-aware component through mapping, the 3D DRC engine evaluates it as a physical enclosure for collision purposes rather than a net-intelligent electrical object with pin-specific connectivityhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66190/what-s-your-fastest-way-to-unfix-fixed-objects-in-allegro-pcb-editorWed, 22 Jul 2026 14:44:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:856b36c9-a4f1-45fe-9d93-e00c70aa88ddElectro NodeHello All, This is a very simple one. We've all experienced it. After fixing dozens of components and traces to protect completed work, a major design change requires moving large sections of the board. Manually unfixing everything can be time consuming and frustrating. How do you handle this situation in Allegro PCB Editor? Do you use a favorite shortcut, command, or SKILL script to speed up the process? Please share your tips and best practices with me so I can save a lot of time. Thanks!Allegro X PCB EditorTipsPCB designunfixhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66168/from-challenges-to-solution-interactive-3dx-canvas-session---join-us-on-july-22nd/1408962Wed, 22 Jul 2026 11:03:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6799c2e4-6273-4e7f-bfd0-ec0508515091vidhyaparameswariThank You for Joining! Thank you all for your active participation and engaging questions throughout this session. Although the live session has concluded, the forum will remain open. Please feel free to continue posting your questions, and we will be happy to respond and assist you. I appreciate your time and look forward to continuing the discussion!https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66168/from-challenges-to-solution-interactive-3dx-canvas-session---join-us-on-july-22nd/1408963Wed, 22 Jul 2026 11:03:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f6e08f79-ab37-42ed-9cc7-f50d2ff21193EnthuEDAOkay …. When importing a 'deformed' STEP model from an external solver back into Allegro 3DX Canvas, how does the 3D DRC engine handle net-aware collision checking? Does the imported STEP retain component and pin-level net intelligence, or is it evaluated strictly as a passive mechanical keepout enclosure?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66168/from-challenges-to-solution-interactive-3dx-canvas-session---join-us-on-july-22nd/1408961Wed, 22 Jul 2026 10:57:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6105076b-15ee-4012-a737-c68138871683techiecsIn Allegro X PCB Editor, automated pin-to-port mapping for high-pin-count and asymmetric devices is handled through the Signal Model Assignment interface and the Device Modeling Language (DML) framework. Additionally, Thank you for your question. I believe that this appears to be related to the Sigrity/SystemSI product area and would benefit from the expertise of the dedicated Sigrity team. I would recommend posting your question on the Cadence Sigrity Forum https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity , where a domain expert will be able to review your query and provide the most accurate guidance.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66168/from-challenges-to-solution-interactive-3dx-canvas-session---join-us-on-july-22nd/1408960Wed, 22 Jul 2026 10:46:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ca9dac2d-3894-42aa-9b58-933bae6a05c8EnthuEDAThank you … a follow up question is …. Since signal assignment relies on ⁠ Analyze > Model Assignment ⁠ , how does Allegro manage automated pin-to-port mapping for high-pin-count, asymmetric S -parameter matrices or multi-gigabit differential pairs without manually assigning each net interface in Sigrity / SystemSI?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66168/from-challenges-to-solution-interactive-3dx-canvas-session---join-us-on-july-22nd/1408959Wed, 22 Jul 2026 10:46:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:91c6e8aa-2d6e-4af9-9fdd-b11a9381acc4techiecsIn Allegro X PCB Editor, while there may a tight integration with the Celsius Thermal Solver for thermal analysis, there is currently no automated, bi-directional workflow to re-import a calculated thermal deformation mesh data directly into the 3DX Canvas for automated 3D DRC. If an external solver (like Celsius or an MCAD tool) calculates a deformed state due to CTE or mechanical stress, that state can be exported as a STEP file. You can then try to re-import this "deformed" STEP model into Allegro as a mechanical component or enclosure. The 3D DRC engine in 3DX Canvas can then evaluate clearances between your PCB components and this deformed geometry. IDX Flow: For complex mechanical changes involving outlines, zones, and bends, the IDX flow is the recommended method for bi-directional data exchange between Allegro and mechanical tools.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66168/from-challenges-to-solution-interactive-3dx-canvas-session---join-us-on-july-22nd/1408958Wed, 22 Jul 2026 10:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:239e694e-294c-4a6f-8915-714126dbcf6cvidhyaparameswariIntegrating 3D DRC clearance rules directly into the Constraint Manager database is a best practice for achieving real-time spatial feedback in Allegro X PCB Editor, especially for complex 16+ layer boards with extensive mechanical STEP models. Constraint Manager Setup: You can specify 3D clearance values for horizontal and vertical spacing between components directly in the 3D domain of Constraint Manager. Navigate to Setup – Constraints – Constraint Manager. Under the 3D domain, expand the 3D Clearance folder. Create a new CSet (Constraint Set) and define the required clearance values for different component categories (e.g., mechanical, connector, discrete, BGA). DFA Device Classes: To optimize performance and reduce latency on complex boards, group symbol definitions that share the same clearance values using the DFA_DEV_CLASS property. This allows a single class entry in the spreadsheet to manage rules for multiple symbol instances (e.g., all 0805 packages), simplifying the database and accelerating real-time checks. Geometry Selection: When defining 3D spacing checks, you can select specific geometries to check, such as 3D CAD models (STEP) against other 3D models or board elements. By default, the system checks the 3D CAD model against the 3D CAD model if mapped.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66168/from-challenges-to-solution-interactive-3dx-canvas-session---join-us-on-july-22nd/1408957Wed, 22 Jul 2026 10:40:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:526d3500-976a-4b2d-85a0-8c6b4f820a8ctechiecsIn Allegro X PCB Editor, the Signal Model Assignment tool (accessed via Analyze > Model Assignment) is the primary interface for mapping IBIS and SPICE models to components and their pins. While the Model Mapper being referred to here is the one which is used in 3DX Canvas that enhances the process of mapping 3D models to PCB components.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66168/from-challenges-to-solution-interactive-3dx-canvas-session---join-us-on-july-22nd/1408956Wed, 22 Jul 2026 10:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:60c910d3-3bb1-480b-b84a-40b9418b6525EnthuEDASince CTE and material deformation require dedicated external solvers, is there a streamlined or automated bi-directional workflow (such as via IPC-2581 or Celsius) to re-import calculated thermal deformation mesh data back into the 3DX Canvas so 3D DRC can be run against the actual deformed state?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66168/from-challenges-to-solution-interactive-3dx-canvas-session---join-us-on-july-22nd/1408955Wed, 22 Jul 2026 10:35:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:4fc23fdb-8b9c-4b82-9d67-15cbf0e11348vidhyaparameswariThe system manages spatial collisions by checking 3D CAD models or component shapes which is Place Bound/DFA Bound against each other. We have Component to Rigid-Flex checks available which checks models or shapes of a component against the outer surface of a rigid-flex. Dynamic Bends: The 3D DRC engine accounts for the bend state of the flex substrate. For example, if a flex portion is bent, the system measures the vertical distance from the component to the flex surface. If the clearance is insufficient, you can resolve the DRC by interactively changing the inner radius of the bend, which repositions the flex portion in 3D space For Thermal Expansion (CTE) and Deformation States, While the 3DX Canvas is highly effective at evaluating clearances in different deformation states (such as bent vs. flat flex substrates), the standard 3D DRC engine primarily focuses on geometric clearances based on the current physical state of the design. Deformation State: The system evaluates DRCs based on the specific bend parameters defined in the design. It does not natively simulate real-time material deformation or thermal expansion (CTE) within the 3D DRC check itself. Inter-Layer DRC: For rigid-flex designs, you can use Inter-Layer DRC to check for overlaps or spacing requirements between different material classes (like stiffeners and masks) that are critical for fabrication and assembly. For advanced thermal expansion or stress analysis, you would typically export the 3D representation of the design from the 3DX Canvas to a dedicated simulation tool.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66168/from-challenges-to-solution-interactive-3dx-canvas-session---join-us-on-july-22nd/1408954Wed, 22 Jul 2026 10:32:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2d802fa0-a427-42eb-92bd-40493d0b084aEnthuEDAIs there a recommended best practice for integrating 3D DRC clearance rules directly into the Constraint Manager database so that dynamic shape updates trigger real-time 3D spatial checks without causing noticeable latency on complex 16+ layer boards with extensive mechanical STEP models?