https://community.cadence.com/cadence_technology_forums/pcb-design/en-USTelligent Community 13https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66208/how-do-i-use-the-tcl-command-to-save-an-image-and-a-visio-drawing-file-from-a-dsn-file-as-a-new-file/1409163Thu, 13 Aug 2026 16:10:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e634941e-76b9-40ed-907d-542be249ac2dTechnoBobbyHi FK202606088435 , To retrieve the text content, you can try: set lObjs [GetSelectedObjects] set lComment [$lObj GetDboCommentText] set txt [DboTclHelper_sMakeCString] $lComment GetText $txt puts "Text: [DboTclHelper_sGetConstCharPtr $txt]" You can also iterate through the effective properties of the selected text object which will return text, bounding box, font name, etc: proc EffectivePropsAll {lObject} { set lStatus [DboState] set lPropsIter [$lObject NewEffectivePropsIter $lStatus] set lPrpName [DboTclHelper_sMakeCString] set lPrpValue [DboTclHelper_sMakeCString] set lPrpType [DboTclHelper_sMakeDboValueType] set lEditable [DboTclHelper_sMakeInt] set lStatus [$lPropsIter NextEffectiveProp $lPrpName $lPrpValue $lPrpType $lEditable] while {[$lStatus OK] == 1} { puts "[DboTclHelper_sGetConstCharPtr $lPrpName] = [DboTclHelper_sGetConstCharPtr $lPrpValue]" set lStatus [$lPropsIter NextEffectiveProp $lPrpName $lPrpValue $lPrpType $lEditable] } delete_DboEffectivePropsIter $lPropsIter } EffectivePropsAll [GetSelectedObjects] Hope this helps!https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66255/request-for-allegro-board-file-to-ascii-conversion-guidance/1409162Thu, 13 Aug 2026 16:01:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1491cef9-6d60-46c3-8240-1588d6d49593DH202601057529I think the only supported file format is IPC2581https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66259/how-to-use-tcl-commands-to-retrieve-text-content-and-formatting-from-a-circuit-diagram-page/1409161Thu, 13 Aug 2026 15:29:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:cd9bc1ae-abea-41d8-9ba4-08d297ae7224CadAPTry below api for text fontsize and fontname. DboTclHelper_sMakeLOGFONT(lfFaceName, lfHeight, lfWidth, lfEscapement, lfOrientation, lfWeight, lfItalic, lfUnderline, lfStrikeOut, lfCharSet, lfOutPrecision, lfClipPrecision, lfQuality, lfPitchAndFamily) : returns LOGFONT For example, setting text arial and text size 10 set fntpbj [ DboTclHelper_sMakeLOGFONT "Arial" 16 0 0 0 400 0 0 0 0 7 0 1 16]https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66261/creating-manufacturing-outputs-made-easyThu, 13 Aug 2026 05:43:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:5108ea17-e223-4a8c-b79d-dc341a25fba4Renu VibhaAre you confident in generating accurate Film Control Records and Gerber files for your PCB designs? This video demonstrates the creation of artwork film control records and gerber files from within the Allegro X PCB Editor How to create Film Control Records and Gerber Files from within the Allegro X PCB Editorhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66259/how-to-use-tcl-commands-to-retrieve-text-content-and-formatting-from-a-circuit-diagram-pageThu, 13 Aug 2026 01:47:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ed7b42d9-39af-493e-a032-d6518af56ee0FK202606088435Hi, Regarding retrieving the text content and formatting from a circuit page using TCL commands, I need the text content, text size, font, and font style. I'd like to ask if there are TCL commands that can extract the same information as in File→Export→Design XML in the following UI interface? Below is an example of an error I encountered when trying to retrieve font format, text size, and text font: # Retrieving LOGFONT object index (but pure TCL cannot parse its internal fields) set lFont [DboGraphicCommentTextInst_sGetFont $lTextInst $lStatus] Best Regards,https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66219/join-us-for-our-next-live-ask-me-anything-session-on-constraint-manager-your-questions-expert-answers/1409159Wed, 12 Aug 2026 11:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:281dbd3c-159c-401b-a81f-bc232c27ac53VipulcThank you for the great questions and engagement today.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66219/join-us-for-our-next-live-ask-me-anything-session-on-constraint-manager-your-questions-expert-answers/1409158Wed, 12 Aug 2026 10:55:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:66842f32-a161-43e9-b30d-0f2315e2b218VipulcYes. You can explicitly create pin pairs by selecting a net or Xnet in the Constraint Manager, right-clicking, and choosing Create > Pin Pair . You then select the driver and receiver pins.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66219/join-us-for-our-next-live-ask-me-anything-session-on-constraint-manager-your-questions-expert-answers/1409157Wed, 12 Aug 2026 10:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:34fa3f0e-1474-46a3-a678-40f358bf98e1CF202606104231Can you manually create pin pairs for specific constraints ?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66219/join-us-for-our-next-live-ask-me-anything-session-on-constraint-manager-your-questions-expert-answers/1409156Wed, 12 Aug 2026 10:48:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:dc41238a-0253-416a-bbd8-67ecbd918ab0VipulcConstraint Manager can automatically generate pin pairs based on the CLASS property of the component and the PINUSE property of the pins. Incorrect settings for these properties can lead to unexpected pin pair generation.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66219/join-us-for-our-next-live-ask-me-anything-session-on-constraint-manager-your-questions-expert-answers/1409155Wed, 12 Aug 2026 10:43:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2dd58994-ecf8-49ae-96b9-70d0eaea15a9CF202606104231How does the tool handle pin pair creation for wiring and delay constraints?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66219/join-us-for-our-next-live-ask-me-anything-session-on-constraint-manager-your-questions-expert-answers/1409154Wed, 12 Aug 2026 10:41:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:10c8e6ac-7fcf-4eb6-8f79-822dc3522fa2VipulcWhen enabled, differential pair overrides have a higher precedence than constraint regions. This is automatically applied if properties like DIFFP_PRIMARY_GAP or DIFFP_NECK_GAP are attached to the differential pair.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66219/join-us-for-our-next-live-ask-me-anything-session-on-constraint-manager-your-questions-expert-answers/1409153Wed, 12 Aug 2026 10:34:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:97eab75d-e1fd-47b4-8e07-3ea44c111718CF202606104231What happens to constraint precedence when differential pair overrides are used?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66219/join-us-for-our-next-live-ask-me-anything-session-on-constraint-manager-your-questions-expert-answers/1409152Wed, 12 Aug 2026 10:28:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:30a53910-95ba-4d50-8a14-32764190ee73VipulcYou can hide them by using the Objects > Filter menu in Constraint Manager and disabling the PinPair Result checkbox.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66219/join-us-for-our-next-live-ask-me-anything-session-on-constraint-manager-your-questions-expert-answers/1409151Wed, 12 Aug 2026 10:20:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d54af51a-4ab2-4abc-8998-e9e558eace59CF202606104231how can you hide RePP objects if they clutter the worksheet?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66219/join-us-for-our-next-live-ask-me-anything-session-on-constraint-manager-your-questions-expert-answers/1409150Wed, 12 Aug 2026 10:16:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:5ee28872-8412-472e-ade8-39b46badbf6fVipulcThe Wiring worksheet is used to define topology scheduling parameters. This includes physical rules like Stub Length and electromagnetic interference (EMI) rules such as Max Exposed Length.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66219/join-us-for-our-next-live-ask-me-anything-session-on-constraint-manager-your-questions-expert-answers/1409149Wed, 12 Aug 2026 10:08:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c9e569e6-e957-4f99-83af-dcbd3f5f0648CF202606104231What is the purpose of the wiring worksheet in the electrical domain?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66219/join-us-for-our-next-live-ask-me-anything-session-on-constraint-manager-your-questions-expert-answers/1409148Wed, 12 Aug 2026 10:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f872e7f1-927d-4fa9-a94d-71decc4124d3VipulcWelcome everyone and thank you for joining today’s Expert Session. Please feel free to post your questions any time—we’re here to help.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/62715/skill-check-for-shape-minimum-aperture-of-gap-width/1409147Wed, 12 Aug 2026 09:54:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2e454487-d48b-465a-8b84-d36557acfd73TL202608111936Hi, I don't know if you've resolved your problem yet, but I have an idea: - Select the shape → extract the shape's voids → convert each void into a polygon → expand the polygon → select the other voids or shape segments by using axlAddselectbyPoly→ measure them. Luanhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66219/join-us-for-our-next-live-ask-me-anything-session-on-constraint-manager-your-questions-expert-answers/1409146Wed, 12 Aug 2026 09:48:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8d2309ac-ca11-44de-88da-93ddf5cb0045Renu VibhaHi Community Users, We start the session in another 15 minutes, looking forward to connecting with you all and answering your questions. Feel free to start dropping your queries now.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/51534/skill-program-to-save-user-colors/1409145Wed, 12 Aug 2026 09:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:312b467b-8f62-4faf-a44c-57038e75051dTL202608111936Hi Soll, It is simplest way to do that. According to the Allegro documentation, File → Export → Parameters ( param out ) allows you to create a .prm file, which can then be imported back using param in . Luan