https://community.cadence.com/cadence_technology_forums/Network with other Cadence users and Cadence technologists...en-USTelligent Community 13https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/74682/controlling-accessibility-of-components-when-place-component-in-schema/1434883Fri, 02 Oct 2026 06:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0ebe4bcc-3b26-4464-a8e1-958f4bc1311fMZ20250602835Dear rg13, may i ask if it is possible to use/define color within unified search similar as DEHDL? Best Regards Moyanhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/70350/how-to-create-a-design-file-in-capture-using-tcl/1434882Fri, 02 Oct 2026 05:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:716dcb29-1ab7-46ca-b5b7-a7dc3c4415cdPatEscherThe easiest way is to create the opj file manually through tcl. proc InitializeOpj {libraryName} { # initialize opj if not exists yet set base [regsub "(.*)(\.olb)" $libraryName "\\1"] set opjPath "$base.opj" set fexist [file exist $opjPath] if {!$fexist} { set filename [file tail $libraryName] set opjContent [open "$opjPath" "w"] puts $opjContent {(ExpressProject ""} puts $opjContent { (Folder "Design Resources"} puts $opjContent { (Folder "Library")} puts $opjContent " (File \".\\$filename\"" puts $opjContent { (Type "Schematic Library"))} puts $opjContent { (DOCKED "TRUE")} puts $opjContent { )} puts $opjContent {)} close $opjContent } }https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/70350/how-to-create-a-design-file-in-capture-using-tcl/1434880Thu, 01 Oct 2026 21:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b73827a9-49ff-4e5d-a64e-1c23d1e73754digital1Hi TechnoBobby Thank you that worked however this bit i didnt like # Open the DSN in Capture Open {C:/path/to/DboTest.dsn} although it worked it gave me a dialog box to click ok on is there any way it can be done without this dialog box. Other than that im happy with the resulthttps://community.cadence.com/cadence_technology_forums/c-sup/f/c-sup-welcome/74684/hifi5-naturedsp-rfft-output-scaling-issue-for-different-fft-sizesThu, 01 Oct 2026 14:37:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0478eb88-d1f3-4a23-8e6e-82031260b78eBR202501213237Hi, I am working on standalone RFFT testing on Xtensa HiFi5 using the NatureDSP library. I am testing different FFT sizes and comparing the fft_real32x32() output against my reference FFT data. I am seeing the FFT output matches for 128, 512 and 2048 points , but does not match for 64, 256 and 1024 points . My question is: How should I correctly interpret/compensate the RFFT output for different FFT sizes and the returned fft_shifts value? Is there any additional normalization or scaling required when comparing the HiFi5 fft_real32x32() output with a floating-point/reference FFT? Also, has anyone observed this kind of behavior where:T he FFT output matches for 128, 512 and 2048 points with fft_real32x32() / ifft_real32x32() on HiFi5? Any guidance on the correct FFT/IFFT scaling interpretation would be appreciated. Platform: Xtensa HiFi5 Library: NatureDSP HiFi5 Functions: fft_real32x32() / ifft_real32x32() Scaling option: 3 Thanks.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/70341/airgap-is-reduced-after-uprev/1434849Thu, 01 Oct 2026 11:21:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:019db0a1-5030-46e5-a0a6-68ee890be5e8mahimagHi Siri , After the update, have you tried running Database check (Tools > Database Check) once? Also, make sure the shapes are up to date. If it is still an issue, I might need to look at the database. Let me know if you can share the database and I can contact you through separate channel.https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/74683/netlist-errorThu, 01 Oct 2026 08:58:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1080a526-431a-4128-9997-2a34b3cf5efeDA202602028132Hello I am currently running a test containing emx extraction (s param file) How have I assembled the test ? to do so, I have created schematic and schematic_emx cellviews schematic_emx just has instance analogLib/nport with s param file attached schematic is just a schematic (metal resistors etc) To run the test, I have assigned schematic_emx cellview in corner setup (and not the schematic cellview) How have I run the test ? I have created testbench schematic (in ADE assembler, right click on the test Netlist>Create... or Netlist>Recreate...), using the schematic cellview, not the schematic_emx cellview, which was successful Then I have proceeded to run the simulation (using the schematic_emx cellview according to corner setup) and got netlist error, because the schematic_emx was not checked & saved My question is - How can I define the Netlist>Create... (or Netlist>Recreate...) to create the netlist according to the corner setup? Thanks DanielADE ADEXLADEEMXSchematicADE Assemblerhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/74682/controlling-accessibility-of-components-when-place-component-in-schema/1434846Thu, 01 Oct 2026 08:01:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:debbed1d-89a2-4101-9aed-0f1b45b9ea1dMZ20250602835Dear rg13, many thanks for your prompt reply, Many thanks Moyanhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/70350/how-to-create-a-design-file-in-capture-using-tcl/1434845Thu, 01 Oct 2026 07:57:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f2842d40-d998-49e0-949c-13511d5c1998TechnoBobbyHi digital1 , Since the design is being created through the Dbo API, and it is not being opened as a Capture project, so the OPJ and Project Manager views are not initialized until the design is reopened. You can either use the GUI commands to create the project, or continue with the Dbo approach and reopen the design for doing further processing. To discover the GUI commands, enable journaling in the Capture Command Window: SetOptionBool Journaling TRUE Then manually create a project and review the recorded commands. If you would like to continue with your current approach, then after saving the design, remove the design from the session using below commands: $lSession RemoveDesign $lDesign # Delete the session DboTclHelper_sDeleteSession $lSession # Open the DSN in Capture Open {C:/path/to/DboTest.dsn} And then continue all further processing on the design opened. Hope this helps!https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/74682/controlling-accessibility-of-components-when-place-component-in-schema/1434844Thu, 01 Oct 2026 07:35:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:88ecd1c7-c0b3-49fa-a6f7-2a2d722225cfrg13Yes, this solution used to work in DEHDL. However, for standalone System Capture, you can develop TCL script which can show kind of warning/error based on status of the part from Unified search part row. If System Capture client is connected to Pulse server through PULSE_REMOTE_URL then Lifecycle status can be configured in search.config for such requirement. You can refer below: pmlauth/pmlauth25.1/Configuring_Lifecycle_Status.htmlhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/74682/controlling-accessibility-of-components-when-place-component-in-schemaThu, 01 Oct 2026 07:11:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6c0d0061-ae52-46ac-a1b3-2ce2745c1837MZ20250602835Dear All, in DE HDL, i can restrict the availability of some components with using The Search_Result_Highlight_Attr_Name directive in the project .cpm file to specify the attribute name for highlighting search results in the Component Browser, to define which attribute's values will trigger specific actions, such as highlighting or generating warnings/errors for components based on their status., For example, disable the addition of these physical parts which have the status "in active"; Or give a warning if try to add a not preferred part in design. May i ask are there similär function availble in system capture? Or How could i achive the funtion after i select a part within Unified Search, the status of the Part will be checked and showed kind of warning/error based on status of the part with using the TCL script? comp_browser/comp_browser17.4-2019/2_configure_comp_browser.html#pgfId-1052684 How can I highlight two attribute values in Component Browser from a single attribute name in project .cpm file? Best Regards Moyanhttps://community.cadence.com/cadence_technology_forums/f/awr-design-environment/74681/importing-matlab-5g-nr-waveforms-into-vssThu, 01 Oct 2026 02:48:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:af4b0a7a-8dbf-428d-b9fd-070b340bc890AnalogMonkI generated a 5G NR baseband IQ waveform using the MATLAB 5G Toolbox and saved it as a .mat file. Can this waveform be imported directly into VSS and used as the signal source for a complete transmit/receive chain simulation? If direct .mat file import is not supported, what is the recommended workflow for transferring MATLAB-generated 5G NR waveforms into VSS for testing and validation?5GawrVSShttps://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/70343/placing-a-dock-window-to-left-of-layout-screen-above-the-layer-palette/1432837Wed, 30 Sep 2026 09:36:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7f0c968f-8351-4c02-9bf9-07f7abda4b34blankmanHi Andrew, that is myself, my apologies, I had forgotten about this past log. Will update latest case. Kind regardshttps://community.cadence.com/cadence_technology_forums/f/awr-design-environment/74337/awr-community-poll-which-awr-workflow-would-benefit-most-from-aiWed, 30 Sep 2026 05:04:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:5e707fbd-d08a-435a-bc08-7da8558dab04CM20260602798If AI could save you the most time in AWR, which capability would have the biggest impact on your workflow? A) EM Optimization & Design Closure Automatically refine layout dimensions and EM parameters to meet performance targets with fewer simulation iterations. B) Intelligent Matching Network Synthesis Generate optimized input/output matching networks based on gain, bandwidth, linearity, and efficiency requirements. C) Multi-Objective RF Design Tuning Simultaneously optimize competing specifications such as gain, PAE, output power, noise figure, and stability. D) Yield & Manufacturing Robustness Analysis Identify critical sensitivities and recommend design improvements to maximize production yield. What consumes the most engineering time in your RF workflow today, and why? Share your thoughts in the commentsMWOAIforEngineeringRF & MicrowaveawrEM simulationRF designAWRDEAIforRFhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/74336/extract-areas-on-the-fpcb-that-do-not-contain-arcs-season2Wed, 30 Sep 2026 02:36:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6f4c138c-0f78-409e-ac57-11e8e32b1294SG20260713408Hello, everyone. I am reposting this with the finalized code, which builds upon the code shared by "Hoangkhoipcb". Once again, I would like to thank "Hoangkhoipcb". /* ================================================================================ * (26Y/09M/30D) * Command : create_arc_chk * Function : Checks for bent corners (sharp angles) without arcs on CLINES. * Highlights detected segments and generates a report log. * * [How to Use] * 1. Modified to allow checking of individual layers or all layers. * 2. When the window appears after execution: * 3. Select the layer you wish to check and click the OK button. * - All_Layer : Checks clines on all layers. * - Others : Checks clines only on the specific layer. * 4. Clicking the Cancel button stops the operation. * * Output File : create_arc_chk.log ================================================================================ */ axlCmdRegister("create_arc_chk" 'create_arc_chk) (defun create_arc_chk () (let (all_layers sel_layer clines seg_list Out_file segs seg next_seg angle pt_corner error_count) all_layers = append(list("All_Layer") axlSubclassRoute(?field 'isEtch)) sel_layer = nth(axlUIMultipleChoice("Select a Layer" all_layers "All Etch Layer") all_layers) when(sel_layer if(sel_layer == "All_Layer" then axlSetFindFilter(?enabled '("noall" "CLINES" "INVISIBLE") ?onButtons '("all")) axlAddSelectAll() clines = axlGetSelSet() else axlVisibleDesign(nil) axlVisibleLayer(strcat("ETCH/" sel_layer) t) axlVisibleLayer(strcat("PIN/" sel_layer) t) axlVisibleLayer(strcat("VIA CLASS/" sel_layer) t) axlVisibleLayer("BOARD GEOMETRY/OUTLINE" t) axlVisibleUpdate(t) axlSetFindFilter(?enabled '("noall" "CLINES") ?onButtons '("all")) axlAddSelectAll() clines = axlGetSelSet() ) axlClearSelSet() seg_list = nil error_count = 0 Out_file = outfile("create_arc_chk.log" "w") fprintf(Out_file "%-5s %-7s %-10s %s\n" "No" "Angle" "Layer" "Location") foreach(cline clines segs = cline->segments while(cdr(segs) seg = car(segs) next_seg = cadr(segs) /* Proceed only if both segments are straight lines */ if(seg->xy == nil && next_seg->xy == nil then /* Find the intersection point of two consecutive line segments */ if(axlGeoPointsEqual(car(seg->startEnd) car(next_seg->startEnd)) || axlGeoPointsEqual(car(seg->startEnd) cadr(next_seg->startEnd)) then pt_corner = car(seg->startEnd) else pt_corner = cadr(seg->startEnd) ) angle = abs(axlRadToDeg(axlGeoAngleBetweenLines(seg->startEnd next_seg->startEnd))) if(!axlGeoEqual(angle 0.0) && !axlGeoEqual(angle 180.0) then error_count = error_count + 1 fprintf(Out_file "%-5d %-7.2f %-10s %L\n" error_count angle cadr(parseString(seg->layer "/")) pt_corner) seg_list = cons(seg seg_list) seg_list = cons(next_seg seg_list) ) ) segs = cdr(segs) ) ) close(Out_file) if(error_count > 0 then axlHighlightObject(seg_list) axlUIViewFileCreate("create_arc_chk.log" "Arc Segments Check" nil) printf("### Errors : %d ###\n" error_count) else printf("### No arc-less corners found. ###\n") ) ) ) )https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/70345/question-on-skill-code-for-cadence-official-mos-pcell/1424879Wed, 30 Sep 2026 01:36:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:fddb89f9-c95f-4309-b21a-f49ea06bda84SZ20260803361Hi Andrew, Thank you so much for taking the time to look into this and give such a detailed explanation! Now I understand the big picture: this sample has a complete framework to add device definitions into the tech library. I also get why the code only adjusts rightStretch for substrate tie abutment. That makes sense now. I will check out the PCell Designer video you shared. Thanks again for your patient help! Best regards, Stevehttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/70350/how-to-create-a-design-file-in-capture-using-tclTue, 29 Sep 2026 20:48:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:82879552-07ed-4f6b-a5c0-8107be8ac347digital1Im trying to create a design in capture programatticaly using tcl here is my code so far # Get the existing DboSession set lSession $::DboSession_s_pDboSession DboSession -this $lSession # Create a DboState set lStatus [DboState] # Build a test directory underneath the Capture workspace set workspace [::orcad::startpage::getCapWorkspacePath] set projectsDir [file join $workspace "projects"] set testDir [file join $projectsDir "DboTest"] file mkdir $testDir # Define the design name/path set designPath [file join $testDir "DboTest.dsn"] set rootName "DboTest" # Create CString objects for the CreateDesign API set designNameCString [DboTclHelper_sMakeCString] DboTclHelper_sSetCString $designNameCString $designPath set rootNameCString [DboTclHelper_sMakeCString] DboTclHelper_sSetCString $rootNameCString $rootName # Create the DboDesign set lDesign [$lSession CreateDesign $lStatus $designNameCString $rootNameCString] # Get the root DboSchematic set lRootSchematic [DboDesign_GetRootSchematic $lDesign $lStatus] # Create the first schematic page set pageNameCString [DboTclHelper_sMakeCString] DboTclHelper_sSetCString $pageNameCString "Page 1" set lPage [$lRootSchematic NewPage $lStatus $pageNameCString] # Save the Dbo design DboSession_SaveDesign $lSession $lDesign although this saves the design file it does not save it as an opj file as well also there is no file view or hierarchical view in the capture window. i have to exit out of capture and load the design file this creates the opj file and also creates the view window with the file and hierarchical view Is there anyone out there that may know what i am doing wrong Im doing the code in bits and pieces the end result is a kicad file importer for not only capture but later for pcb Im doing this because kicad imports Altium Binary and CadStar binary format files and also has a pretty good gerber to pcb reverse engineering tool so i can save legacy files that we have lost the design tools forOrCAD Capturetclscripthttps://community.cadence.com/cadence_technology_forums/f/custom-ic-design/70349/create-bus-labels-from-csv-fileTue, 29 Sep 2026 19:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:431895e9-2137-45b9-83cf-19633566baf1Darrell LWe have a digital control circuit that uses 1232 hardwired inputs to set the trim values for an RF circuit. The hardwired inputs are organized as 176 busses with 7bits each. After simulation and lab testing, we will have a csv file with the optimum values for each bus. I would like to have some automated way to label the bus connections to each input based on a csv file values. IE if the csv file has 1001000 for bus x, and 0110011 for bus y, then I want some way to label the wire connected to bus x '1,0,0,1,0,0,0", and bus y "0,1,1,0,0,1,1". Is there any way to do this? Alternatively, is there some way to create a schematic block with labeled wires and pins based on the csv file? I could then place that block in the main schematic to set all the trim values. Thanks in advance, Darrellhttps://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/70343/placing-a-dock-window-to-left-of-layout-screen-above-the-layer-palette/1421122Tue, 29 Sep 2026 18:45:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:dde026fc-a68c-40d9-8a8b-935f7b259dc5Andrew BeckettI see you logged a support case about this (47030722) - at least I assume it's you because the wording is identical. You also logged a support case in November 2023 on the same topic (46745168) for which CCR #2906238 was filed. That hasn't been resolved yet (note, I didn't test it myself - as there's an AE already working on this I like to avoid double working). Andrewhttps://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/70345/question-on-skill-code-for-cadence-official-mos-pcell/1421121Tue, 29 Sep 2026 18:12:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:745ce4ef-b4d5-44b0-8f40-027fc10a9e22Andrew BeckettOK, I took a look. The code is fairly complicated - it contains a whole load of infrastructure to install and configure various devices by adding extra information into your tech file and then installing the devices in the tech library too. To set up, you'd use: setSkillPath(cons(prependInstallPath("samples/ROD/rodPcells") getSkillPath())) load("install/spcLoadInstall.il") and then interact with the UI. You have to select the devices you want, choose the appropriate layers to use, and then fill in any missing design rule info that can't already be found in the tech file (sometimes these might be because of table rules). The code is not being maintained and it's just a sample - whether you'd want to start from this or not is another matter. I'd probably recommend using PCell Designer instead if you can get access to it - see this video: Creating a Simple MOSFET with PCell Designer To answer your questions: It's a little unusual, but having an empty then within an if/then/else is OK. It potentially makes it simpler to edit in the then part if you decide you need it later. The rightStretch and leftStretch parameters are hidden parameters which are then altered by the abutment function when two transistors are abutted. If you've chosen to have the substrate contact enabled at the top/bottom, it may have to adjust the size of the diffusion to allow for these substrate contacts, but it only really needs to do it on one side - and in this case the right side is used. This is (I think) trying to handle the scenario where the substrate contact protrudes beyond the transistor width (in this case it's the overall width of the device, not the width of the gate). That's where you'd have a problem with the substrate contacts hitting each other otherwise, so more space needs to be allowed. Hope that helps! Regards, Andrewhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/70342/skill-error-if-too-many-arguments-missing-then-error-on-running-if-command/1421120Tue, 29 Sep 2026 17:08:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e2331ffc-2374-434e-8ab8-06fb277c9976JuanCRHi David, Yes, this "if" statement is correct. You're following the syntax " if( g_condition g_thenExpression [ g_elseExpression ] )" See above, in the post. If you replace the contents of the "if" by this: [quote userid="524126" url="~/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/70342/skill-error-if-too-many-arguments-missing-then-error-on-running-if-command"]if( order parameters = foreach( mapcar param order (get cdfgData param)) parameters = (getq cdfgData parameters) printf("%L" parameters~>values) )[/quote] then you'll see that sklint will flag the error.