https://community.cadence.com/cadence_technology_forums/Network with other Cadence users and Cadence technologists...en-USTelligent Community 13https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/74786/pdf-export-title-block-issueWed, 11 Nov 2026 20:22:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:02b868a9-4097-4259-b581-70134446c204RC202609179615Hello, When trying to export my schematic design as a PDF, I'm having issues with the title block placement. I have multiple sheets in my design and they vary in sheet size. The issue is that the very first sheet is the smallest and on that page the title block is correctly postioned in the bottom right corner but on the subsequent pages on the PDF, the title block is around the middle or on some larger sheets closer to the upper left hand corner. What I'm noticing is that if I were to align the first page and place it on top of the other pages, aligned with the upper left hand corner, the title blocks are aligned. It's as though the title block postion was locked into the scaling of the first page and it put it there on all the rest of the pages. I tried exporting the PDF with page output size different than default 0 but that didn't fix the issue. Capture CIS 25.1 S050 (4459063) [7/18/2026]Capture CIShttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/74781/how-to-get-flowplan-toggles-to-show-up-on-visibility-panel/1435040Wed, 11 Nov 2026 19:55:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0b29a0b7-945e-453b-a52c-8b54032f5f9fRobert FinleyFor Plan visibility by layer to work, Ratsnest bundles are created without a specific layer assignment(plan). Flowplan mode> Select the bundle, >Edit Bundle Property, >[Enable One Layer] select a layer. Click >[ok] That converts the rants bundle to a Plan line. Several things don't work without an active plan line.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/74781/how-to-get-flowplan-toggles-to-show-up-on-visibility-panel/1435039Wed, 11 Nov 2026 17:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1827cd0f-c48e-42b2-bd27-3a4386fae21fRobert FinleyVery usefui! Thanks! owe you a beer.https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/74748/pspice-for-ti-installation-fails---http-403-forbidden/1435038Wed, 11 Nov 2026 12:22:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:382c995d-a1b1-4ef2-934d-603c0312d614BV20261111817This is still an issue nov 11th. How can this be solved?https://community.cadence.com/cadence_technology_forums/f/digital-implementation/74783/guidance-on-clock-skew-insertion-delay-and-clock-tree-optimization-in-cadence-innovus-ctsWed, 11 Nov 2026 09:48:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:630154e4-645d-4572-a01f-3145e62d6f95NN202609204316How do we calculate and decide the target clock skew and insertion delay for CTS and build an optimal clock tree structure with proper skew groups and balancing in Cadence Innovus?Digital ImplementaionInnovusCTShttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/74781/how-to-get-flowplan-toggles-to-show-up-on-visibility-panel/1435037Wed, 11 Nov 2026 08:53:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f1a8df4c-26e7-4bc1-91e1-13309f919114steveDisplay - Color/Visibility then Visibility Pane tab and Plan is in the list of available classes (top left section). Move it to the Visible classes section.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/65699/cross-probing-accumulating-in-capture-instead-of-synchronizing-to-what-is-currently-selected/1435036Wed, 11 Nov 2026 02:29:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d3bc35cb-8cc6-4d71-ac99-ba1ce0f6845fturrityDuring fast cross-probing between OrCAD Capture and Allegro, when many components are selected in PCB and schematic objects are probed afterwards, XProbe Results keeps retaining the stale PCB selections even after placement completes. The only way to recover is to unselect components page by page in Capture, or reopen the project — the stale entries persist until each one is individually cleared from XProbe Results, causing erratic cross-probe navigation afterward.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/74781/how-to-get-flowplan-toggles-to-show-up-on-visibility-panelWed, 11 Nov 2026 00:23:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f0c20023-e911-4490-a86f-62a519e3af1dRobert FinleyAccording to the "Cadence Allegro High Speed and Design Planning: RAK", I should see...https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/74748/pspice-for-ti-installation-fails---http-403-forbidden/1435035Tue, 10 Nov 2026 16:01:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e409448e-bac6-4316-b690-192dac2dcba4MN20261110661Similar issues experienced on both PSpice and OrCAD. Please advice on what to do nexthttps://community.cadence.com/cadence_technology_forums/c-sup/f/c-sup-champion/74779/congratulations-to-our-october-2026-top-contributor/1435034Tue, 10 Nov 2026 15:48:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1f46e2f8-7176-42b2-8e03-52385b4d2f51John TWell done steve, Very well deserved! The community is definitely getting great benefit for your vast experience and guidance!!https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/74778/hi-i-want-to-perform-a-call-back-for-each-enterpoint-and-want-to-continue-until-esc-is-pressed-please-help-here/1435033Tue, 10 Nov 2026 05:38:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:17e21e37-a016-45a9-bcbe-c3c8185d4b64Andrew BeckettProbably simplest is to use enterPoints() instead of enterPoint(), and then use ?addPointProc to specify the callback to call when each point is clicked. Andrewhttps://community.cadence.com/cadence_technology_forums/c-sup/f/c-sup-champion/74779/congratulations-to-our-october-2026-top-contributorTue, 10 Nov 2026 05:21:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:30f68ff7-8fcf-493c-96a9-00c44c76d3f9Renu VibhaCongratulations to our October 2026 Top Contributor, steve ! With an outstanding 17,984 points , 2,880 impactful posts , 50 verified solutions , and 301 community likes received - what an incredible month of contribution and community impact! But the numbers tell only part of the story. Through his deep knowledge of PCB Design , consistent participation, and willingness to help fellow community members, Steve has played an important role in making the Cadence Community a place where people can learn, collaborate, solve problems, and grow together . Thank you, Steve, for sharing your expertise so generously and for continuing to inspire others. Congratulations on this fantastic achievement, and keep making an impact!https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/74748/pspice-for-ti-installation-fails---http-403-forbidden/1435032Mon, 09 Nov 2026 22:48:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8e33097a-b75c-4f66-9880-cd80f2cf4d61FA202611095715Subject: PSpice for TI installation fails with HTTP 403 on multiple networks Hello Cadence Support Team, I am experiencing the same HTTP 403 Forbidden error while installing PSpice for TI on Windows. The installer fails when attempting to access the following URL: https://pcb.cadence.com/startPages/PSpiceTI_data/TI_URLs.txt I have confirmed the following: The installer displays "Unable to access the URL required for installation." Opening the URL directly in a web browser also returns HTTP 403 Forbidden from CloudFront. I tested the URL using two different network connections, and both returned the same error. Since the issue occurs on different networks and similar cases have been reported by other users, I suspect a server-side access or configuration issue. Could you please confirm whether this issue is being investigated and provide an official workaround or alternative installation procedure? I can provide screenshots and the installer log if needed. Thank you for your assistance.https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/74778/hi-i-want-to-perform-a-call-back-for-each-enterpoint-and-want-to-continue-until-esc-is-pressed-please-help-hereMon, 09 Nov 2026 12:46:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1658e409-f5bb-4c30-99aa-415d11cdbbd3GB202611098410Hi, I want to perform a call back for each enterPoint and want to continue until ESC is pressed, please help here. Below is the portion of my code looks like. procedure(func_test() let(() until(ESC is pressed pt=enterpoint() proc_callback(pt) );until ); );procedure procedure(proc_callback(pt) body of the main function );proceduerhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/74776/how-to-export-markup-comments/1435031Mon, 09 Nov 2026 08:08:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c15b3acf-32d3-47c5-9ddb-857db0d16464B Bruekersapparently the markup data is stored as a Json file in an attachment. att = axlGetAttachment("MARKUP_DB_JSON" 'file) att->data This will give a location of the (temporary) file. This file is a json and includes the view, comments, etc.https://community.cadence.com/cadence_technology_forums/f/digital-implementation/74777/how-does-innovus-calculate-transition-mean-and-sigma-with-ccs-lvf-given-that-liberty-defines-nominal-transition-using-nldm-tablesSun, 08 Nov 2026 16:10:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7bac5835-901d-4d32-ac8e-fdcc6b03dc17YW202511205917Background I am using Innovus 23.32-s091_1 for post-route timing analysis with detailed parasitics and SI. The standard-cell libraries contain both: CCS driver and receiver models rise_transition / fall_transition Early/late ocv_sigma_*_transition Moments-based ocv_mean_shift_*_transition , ocv_std_dev_*_transition , and ocv_skewness_*_transition The library corner is SS, 0.675 V, 125 °C. The Model types section of reportDelayCalculation identifies both the relevant driver and receiver as CCS . What is confusing me The Liberty 2017.06 manual explicitly defines: PDF page 696, printed page 15-14: The nominal value corresponding to ocv_sigma_rise_transition is specified by rise_transition . The nominal value corresponding to ocv_sigma_fall_transition is specified by fall_transition . PDF pages 710-713, printed pages 15-28-15-31: The moments-based LVF syntax also identifies rise_transition / fall_transition as the nominal transition tables. It defines: Code block mean rise transition = nominal rise transition + ocv_mean_shift_rise_transition with the equivalent relationship for falling transitions. However, with CCS and detailed RC, the tool also computes voltage waveforms at the driver output and receiver inputs. I understand that CCS and LVF can be used together. My question is specifically how the LVF statistics, referenced to the nominal transition tables, are applied to the CCS-based waveform calculation. Questions What nominal transition does Innovus use when applying LVF in CCS mode? The value obtained from rise_transition / fall_transition ? A transition measured from a CCS-generated waveform? Or a transformed/calibrated combination of these? Are the following expressions valid, and under what assumptions? Code block Reported transition mean = slew measured from a CCS waveform + LVF mean_shift Reported transition sigma = the interpolated LVF sigma/std_dev table value I have not found documentation establishing these expressions. In particular, the first expression appears to replace the nominal reference explicitly defined by Liberty. If the CCS waveform-based slew differs from the nominal transition table value, how does Innovus map the LVF mean shift and standard deviation to the actual RC-loaded stage? Are they applied as absolute offsets, normalized/scaled, or processed through another statistical model? What is the statistical meaning of the waveforms reported by reportDelayCalculation -waveform in a SOCV/LVF analysis? Are they nominal waveforms, mean-adjusted waveforms, or something else? Can their threshold-crossing times be compared directly with the reported transition mean? Which reports or settings can expose this calculation? I would like to identify the actual LVF tables and lookup coordinates used, the nominal reference, and any statistical propagation or waveform-related adjustments. Example report For the net arc: Code block INV_X3/ZN → detailed RC network → DFHCQHSXG_X4/D reportDelayCalculation -max -si reports: Code block Transitions Rise Fall Input transition (mean): 0.052500 ns 0.057700 ns (sigma): 0.001845 ns 0.001767 ns Output transition (mean): 0.135100 ns 0.134100 ns (sigma): 0.001845 ns 0.001767 ns This is a net arc : "Input transition" refers to the driver output pin, and "Output transition" refers to the receiver input pin—not the cell's input-to-output arc. Could someone point me to the relevant Cadence documentation or explain the calculation? I am trying to reconcile the Liberty-defined nominal reference with the transition mean and sigma actually reported by Innovus , rather than merely confirm that CCS and LVF can coexist.Digital ImplementaioncharacterizationTiming ClosureInnovus.libhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/74751/pspice-for-ti-installer-fails-http-403-forbidden-downloading-ti_urls-txt/1435030Sat, 07 Nov 2026 18:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0e838afa-4bf1-48fe-a44e-fbe9f9a09d80RC20261107966I am experiencing the same problem today.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/74746/using-capture-cis-25-1-using-orcad-x-professional-plus-and-my-license-is-active-and-cloud-access-is-on-but-i-am-told-i-am-offline-and-when-trying-to-use-parts-from-the-library-i-get-an-error-message/1435029Sat, 07 Nov 2026 16:36:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:67899775-6598-48c8-b30a-f566d3866bd2CP202609102340It is still down on my end as well. Nothing seems to have changed yet.https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/74748/pspice-for-ti-installation-fails---http-403-forbidden/1435028Sat, 07 Nov 2026 01:49:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ee9bfd4a-0144-42dc-bf00-71dfaf12dd9eTA202611061545Hello Cadence Support Team, I am experiencing exactly the same issue when trying to install PSpice for TI. The installer fails with an HTTP 403 Forbidden error when accessing the following URL: https://pcb.cadence.com/startPages/PSpiceTI_data/TI_URLs.txt I downloaded the installer from the official TI website on November 7, 2026. I have also seen several reports of the same issue on this forum. Could you please confirm: Is Cadence currently investigating this issue? Is there an estimated timeline for restoring access to the installation server? Is there an alternative download link or installation procedure available? I would appreciate any updates or guidance on how to proceed. Thank you for your support.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/74746/using-capture-cis-25-1-using-orcad-x-professional-plus-and-my-license-is-active-and-cloud-access-is-on-but-i-am-told-i-am-offline-and-when-trying-to-use-parts-from-the-library-i-get-an-error-message/1435027Fri, 06 Nov 2026 21:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:bc417fd6-ae22-4870-8f6a-1a8b998ed0d2TG202408061233I can't access the cloud either and it was supposed to be fixed by now. Seems like this would effect a lot of people and very strange that its been down for so long.