https://community.cadence.com/cadence_technology_forums/Network with other Cadence users and Cadence technologists...en-USTelligent Community 13https://community.cadence.com/cadence_technology_forums/physical-system-simulation/digimat/f/digimat/73884/does-digimat-provide-dedicated-functionalities-for-battery-cell-modeling/1434968Thu, 22 Oct 2026 13:53:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a8d59d6c-697d-4125-9943-d7ac9f723f78BA202610227050What are the update in cell designhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/74733/why-does-ddr5-technology-require-ibis-ami-models-whereas-traditional-ibis-or-spice-only-simulations-were-often-sufficient-for-earlier-ddr-generations/1434967Thu, 22 Oct 2026 10:48:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1e943185-9487-4253-9d86-9d576e552332StephenNewberryB :)https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/74725/looking-for-virtuoso-l-xl-feature-or-skill-that-will-allow-select-by-line-to-select-odd-even-objects/1434966Thu, 22 Oct 2026 09:24:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f9a5d1dd-d361-4006-9ef8-63d99cb262b0Aurel B( inScheme ( defun select_aligned ( @key ( obj ( car ( geGetSelectedSet )) ) ( cv obj -> cellView ) ( direction ' horizontal ) ( modulo 2 ) ( shift 0 ) @rest _ ) "Return objects in CV that have the same master as OBJ and are aligned with it according to DIRECTION. Returned list of objects is filtered by MODULO and SHIFT." ;; Check inputs ( assert ( dbobjectp obj) "select_aligned - ?obj should be a dbobject: %N" cv) ( assert ( and ( dbobjectp cv ) ( equal "cellView " cv -> objType)) "select_aligned - ?cv should be a cellview: %N" cv) ( letseq ( ( x ( xCoord ( lowerLeft obj -> bBox)) ) ( y ( yCoord ( lowerLeft obj -> bBox)) ) ( master obj -> master ) ( index 0 ) ( targets ( cond ( obj -> isAnyInst cv -> instances ) ( obj -> isShape cv -> shapes ) ( t ( error "select_aligned - ?obj should be an instance or a shape: %N %N" obj obj -> objType) ) ) ) ;; Function to check similarity ( is_similar? ( case obj -> objType ( "inst" ( lambda (o) ( eq master o -> master)) ) ( t ( lambda (o) ( equal obj -> objType o -> objType)) ) ) ) ;; Function to check alignment ( is_aligned? ( caseq direction ( ( vert vertical ) ( lambda (o) ( nearlyEqual x ( xCoord ( lowerLeft o -> bBox)))) ) ( ( horiz horizontal ) ( lambda (o) ( nearlyEqual y ( yCoord ( lowerLeft o -> bBox)))) ) ( t ( error "select_aligned - ?direction is not in '( vert vertical horiz horizontal ): %N" direction) ) ) ) ) ;; Filter similar and aligned instance s ( setq targets ( setof o targets ( and (is_similar? o) (is_aligned? o)))) ;; Sort instances by coordinates ( setq targets ( sort targets ( caseq direction ( ( vert vertical ) ( lambda (o0 o1) ( lessp ( yCoord ( lowerLeft o0 -> bBox)) ( yCoord ( lowerLeft o1 -> bBox)))) ) ( ( horiz horizontal ) ( lambda (o0 o1) ( lessp ( xCoord ( lowerLeft o0 -> bBox)) ( xCoord ( lowerLeft o1 -> bBox)))) ) ))) ;; Filter by modulo and shif t ( setq targets ( setof _o targets ( eq shift ( mod index ++ modulo )))) ;; Select resulting objects ( geDeselectAllFig ) ( geSelectFig s targets) )) ) ;SKILL++ ;; Examples ; (select_aligned) ; select even similar objects aligned horizontall y ; (select_aligned ?shift 1) ; select odd similar objects aligned horizontall y ; (select_aligned ?direction 'vert) ; select even similar objects aligned verticallyhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/74720/error-503-service-unavailable-when-searching-for-components/1434965Thu, 22 Oct 2026 06:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e34f727d-a229-4686-ab8f-f31c5cb0f764LF202610219731A 503 usually indicates a server-side or connectivity issue. Since all three providers return 503, check proxy/firewall settings. Also test their websites directly from the same PC. If those work, Capture CIS may have an integration issue. I’d report it to Cadence Support with the 25.1 version.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66348/understanding-the-role-of-config-xml-in-power-topology-analysis/1434964Thu, 22 Oct 2026 06:33:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d9fcad02-11f8-426b-b2ce-4440c28f2247EM202610218420When troubleshooting display issues while using tools like Allegro X System Capture, it’s worth checking that your graphics driver and monitor are configured correctly. If you’re having trouble with available resolutions, the Custom Resolution Utility guide may help you explore supported display modes. Just make sure any custom resolution is compatible with your monitor and graphics driver.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/74733/why-does-ddr5-technology-require-ibis-ami-models-whereas-traditional-ibis-or-spice-only-simulations-were-often-sufficient-for-earlier-ddr-generationsThu, 22 Oct 2026 05:22:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:5457423a-0d20-4372-94c1-ee5c7086a2bcSumithOptions: A. DDR5 operates at lower voltages and therefore requires larger S-parameter files. B. DDR5 introduces receiver and transmitter equalization techniques such as DFE, CTLE, and FFE , which cannot be accurately represented using traditional IBIS models alone. C. DDR5 replaces all channel simulations with transistor-level SPICE simulations. D. DDR5 eliminates the need for signal integrity analysis by using on-die termination.Topology Explorerhttps://community.cadence.com/cadence_technology_forums/f/custom-ic-design/74732/dummy-filling-in-rf-sensitive-areaThu, 22 Oct 2026 01:37:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:77bcbdf6-0207-474a-9328-eac5a11728d6SamanMKDHello everyone, I have a problem with dummy filling. Since my circuit is in the high-frequency range (around 70 GHz), I cannot fill some sensitive parts, including the circuit core, inductor, and Pad space, with dummy fill. As a result, I get PO, OD, and metal density errors in my DRC. What should I do in this case? Do you have any suggestions that can help me, since it is my first tape-out?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/74720/error-503-service-unavailable-when-searching-for-components/1434963Wed, 21 Oct 2026 21:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3cc64dfb-2617-44dd-8e5b-9d50c5e85cc8MB202610216310We have the same problem here, with a Capture CIS 22.1 installation.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/74721/how-to-calculate-actual-value-in-allegro-skill/1434962Wed, 21 Oct 2026 15:23:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c3c239fa-d3a1-4889-93af-428140ecdc5eLF202610219731axlAirGap() does not accurately measure silkscreen text. It often measures text using bounding geometry. DRC instead evaluates the actual rendered text strokes. Cadence recommends creating temporary geometry from the font. Then measure that geometry using axlAirGap() .https://community.cadence.com/cadence_technology_forums/system-analysis/f/clarity-3d-solver/74731/how-to-import-a-brd-file-into-clarity-3d-layout-with-only-selected-nets/1434961Wed, 21 Oct 2026 13:59:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:18c680ea-af11-4aae-b47e-5a4dfcee77a4SumithIn the translator settings, you can enable the "Show Net Selection Dialog" option. This opens the net selection window, where you can choose the nets to import. Another option is to disable all nets and then select only the relevant ones in the Net Manager . This approach is useful when importing all nets.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66346/how-do-we-create-borders-in-system-capture-or-add-our-company-logo-and-other-custom-variables/1434960Wed, 21 Oct 2026 13:21:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:71b3ba55-d41f-4dc2-a538-0b1f6ab9fc00Smith ecadThanks Steve this helps.https://community.cadence.com/cadence_technology_forums/system-analysis/f/clarity-3d-solver/74731/how-to-import-a-brd-file-into-clarity-3d-layout-with-only-selected-netsWed, 21 Oct 2026 13:15:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:63665ba2-853b-4164-91a9-95b08bb460cecistheta07Hi everyone, I am working with a large PCB design in Clarity 3D Layout and need to perform electromagnetic simulation on only a few selected signal and reference nets. When importing the complete .brd file, the design contains many nets that are not relevant to my analysis. Importing the entire design may increase memory usage and simulation time. Is there a way to select only the required nets during board-file import, without importing all the available nets ? If so, could someone share the recommended procedure and any important considerations when selecting signal, power, and ground nets? Thank you in advance for your help!Clarity3DSigrityhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/74730/electrothermal-model-in-mbreakn-or-other-mosfet-modelsWed, 21 Oct 2026 08:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:4351b3b8-df31-43cd-ae12-0473998c576dUS202607259240Hello, I am trying to simulate electrothermal model in MOSFET for MbreakN model found in Pspice, however, I couldn't find a way to connect this component with a self built RC cauer model. I came to an understanding that the dynamic temperature cannot be passed as argument in MbreakN. Is there any way to do this, or any model which already has existing integrated electrothermal coupling where other parameters could be varied arbitarily? I have found some specific industrial models designed for their own products but I want to know if it is possible in some arbitary models. So far I have used ABM to model a simple MOS equation with cauer model connected to it, but this could increase the difficulty when a compact MOSFET model is required. Thank you.captureelectrothermalPSPICEMOSFEThttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/74719/orcad-x-25-1-pro-cant-set-dfa-constraints/1434959Wed, 21 Oct 2026 08:01:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0ba7d250-d3bb-4e8c-9411-dcbc91f164b6steveYou have 2 choices, either add the Silkscreen Top and Bottom layers to the cross section of the PCB. They will then show up under the Mask layers or use the Not in Stackup option (right click - Add subclass group). Here you can make a Silkscreen layer and choose either the classes / subclasses you want to be checked or pick an artwork film.https://community.cadence.com/cadence_technology_forums/f/hardware-software-co-development-verification-and-integration/74727/download-xtensa-software-developer-s-toolkit-sdk-on-trail-evaluation-basis/1434958Wed, 21 Oct 2026 07:49:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:107a7c5d-95e2-43f7-a3f7-7e405dd6438fStephenHHello. You haven't provided much information here so helping you will be tricky. Please send me a private message with the following details, and I will try to connect you with someone from the Tensilica team who can help. Your full name The company you work for Your work email address Your location Thanks. Stevehttps://community.cadence.com/cadence_technology_forums/f/digital-implementation/74729/xcelium-24-03-how-to-get-a-single-setuphold-line-in-annotation-summary-without-separate-setup-hold-rowsWed, 21 Oct 2026 06:57:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ffea37b1-8b75-4e78-bb62-7aa1fd889208TU202610195844After upgrading from Xcelium 24.03 to a release at or after 24.09, I see a change in the SDF annotation statistics. The option -sdf_splitvlog_setuphold appears to be the default now and when I use it in newest versions, I see a warning that this option is deprecated. As far as I can tell, there is no documented option to get the old behavior back. What I see My design uses only combined $setuphold timing checks in the specify block, and the SDF has combined SETUPHOLD entries as well. With -scopewise_sdfstats_log , the statistics table now also lists $setup and $hold as separate rows below $setuphold . In 24.03 only the combined $setuphold row was shown. Minimal reproducer design.sv: module dut (input clk, input d, output reg q); always @(posedge clk) q q) = (1.0, 1.0); $setuphold(posedge clk, d, 0.1, 0.1); endspecify endmodule test.sdf: (DELAYFILE (SDFVERSION "2.1") (DESIGN "dut") (DATE "2026-10-14") (VENDOR "Example") (PROGRAM "Custom") (VERSION "1.0") (DIVIDER /) (VOLTAGE 1.0) (PROCESS "typ") (TEMPERATURE 25.0) (CELL (CELLTYPE "dut") (INSTANCE) (DELAY (ABSOLUTE (IOPATH clk q (1.0:1.0:1.0) (1.0:1.0:1.0)) ) ) (TIMINGCHECK (SETUPHOLD d (posedge clk) (0.1:0.1:0.1) (0.1:0.1:0.1) ) ) ) ) sdf.cmd: SDF_FILE = "test.sdf", SCOPE = tb.u_dut, LOG_FILE = "sdf_annotation.log", MTM_CONTROL = "TYPICAL"; testbench.sv: module tb; reg clk = 0; reg d = 0; wire q; dut u_dut (.clk(clk), .d(d), .q(q)); initial begin #10 clk = 1; #10 clk = 0; #10 d = 1; #10 clk = 1; #10 clk = 0; #50 $finish; end endmodule Compile options: -timescale 1ns/1ps -sysv -sdf_cmd_file sdf.cmd -scopewise_sdfstats_log /dev/stdout Resulting output (relevant part) Path Delays 1 0 1 100.00 $setuphold 1 0.00 1.00 100.00 $setup 1 0 1 100.00 $hold 1 0 1 100.00 The summary lines still say No. of Tchecks = 1 , and annotation is 100%. So I assume this is only a change in the report format and not in simulation behavior. Please correct me if that is wrong. Question Is there a documented (or undocumented) option or setting in the current releases that restores the old reporting/behavior, with combined $setuphold line and no $setup / $hold breakdown (even when I use combined $setuphold both in the .sdf and in the RTL files)?SystemVerilogVerilogxceliumhttps://community.cadence.com/cadence_technology_forums/f/logic-design/74728/xcelium-24-03-how-to-get-a-single-setuphold-line-in-annotation-summary-without-separate-setup-hold-rowsWed, 21 Oct 2026 06:49:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c0d51bf4-a694-4a60-9206-931cf8ff179cTU202610195844After upgrading from Xcelium 24.03 to a release at or after 24.09, I see a change in the SDF annotation statistics. The option -sdf_splitvlog_setuphold appears to be the default now and when I use it in newest versions, I see a warning that this option is deprecated. As far as I can tell, there is no documented option to get the old behavior back. What I see My design uses only combined $setuphold timing checks in the specify block, and the SDF has combined SETUPHOLD entries as well. With -scopewise_sdfstats_log , the statistics table now also lists $setup and $hold as separate rows below $setuphold . In 24.03 only the combined $setuphold row was shown. Minimal reproducer design.sv: module dut (input clk, input d, output reg q); always @(posedge clk) q q) = (1.0, 1.0); $setuphold(posedge clk, d, 0.1, 0.1); endspecify endmodule test.sdf: (DELAYFILE (SDFVERSION "2.1") (DESIGN "dut") (DATE "2026-10-14") (VENDOR "Example") (PROGRAM "Custom") (VERSION "1.0") (DIVIDER /) (VOLTAGE 1.0) (PROCESS "typ") (TEMPERATURE 25.0) (CELL (CELLTYPE "dut") (INSTANCE) (DELAY (ABSOLUTE (IOPATH clk q (1.0:1.0:1.0) (1.0:1.0:1.0)) ) ) (TIMINGCHECK (SETUPHOLD d (posedge clk) (0.1:0.1:0.1) (0.1:0.1:0.1) ) ) ) ) sdf.cmd: SDF_FILE = "test.sdf", SCOPE = tb.u_dut, LOG_FILE = "sdf_annotation.log", MTM_CONTROL = "TYPICAL"; testbench.sv: module tb; reg clk = 0; reg d = 0; wire q; dut u_dut (.clk(clk), .d(d), .q(q)); initial begin #10 clk = 1; #10 clk = 0; #10 d = 1; #10 clk = 1; #10 clk = 0; #50 $finish; end endmodule Compile options: -timescale 1ns/1ps -sysv -sdf_cmd_file sdf.cmd -scopewise_sdfstats_log /dev/stdout Resulting output (relevant part) Path Delays 1 0 1 100.00 $setuphold 1 0.00 1.00 100.00 $setup 1 0 1 100.00 $hold 1 0 1 100.00 The summary lines still say No. of Tchecks = 1 , and annotation is 100%. So I assume this is only a change in the report format and not in simulation behavior. Please correct me if that is wrong. Question Is there a documented (or undocumented) option or setting in the current releases that restores the old reporting/behavior, with combined $setuphold line and no $setup / $hold breakdown (even when I use combined $setuphold both in the .sdf and in the RTL files)?SystemVerilogVerilogxceliumhttps://community.cadence.com/cadence_technology_forums/f/hardware-software-co-development-verification-and-integration/74727/download-xtensa-software-developer-s-toolkit-sdk-on-trail-evaluation-basisWed, 21 Oct 2026 06:31:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e193071a-4e6e-470d-aeed-eac05e36c534RY202609219437Hi, I want to download Xtensa Software Developer’s Toolkit (SDK) on trial evaluation. I have already submitted for to access this tool but have'nt get any approval email yet. Ple helphttps://community.cadence.com/cadence_technology_forums/f/custom-ic-design/74726/vxfi-results-browser-layer-filter-skill-hooksWed, 21 Oct 2026 01:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6a6e55dd-781d-4a25-a747-0844c26aff28IA202606139920Hello, I wanted to know if we have a way using skill to filter layers in vxfi results browser. I looked into this link ( https://ask.cadence.com/ASK/techpub-viewer?xmlName=voltusxfi.xml&title=Voltus-XFi+Custom+Power+Integrity+Solution+User+Guide+--+Filtering+Layers+for+Result+Analysis+-+Filtering+Layers+for+Result+Analysis&c_version=IC26.1&path=voltusXFI%2FvoltusXFIIC26.1%2FFiltering_Layers_for_Result_Analysis.html&pageName=techpub-viewer ) and it's not quite what I'm looking for. This has a way to sync layers with those in palette but when I tried it seems to only work one way, I'm specifically looking into having palette visible layers control vxfi layers or skill hooks for those layers with final purpose of using bindkeys to navigate it. Thankshttps://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/74725/looking-for-virtuoso-l-xl-feature-or-skill-that-will-allow-select-by-line-to-select-odd-even-objectsWed, 21 Oct 2026 00:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b5006d8c-f334-44e3-a3cc-de968db2bd7cFinn HuckleHi Cadence Community, I am using select by line on Virtuoso L/XL. Is there a built in feature that will allow me to select odd/even objects only. For example If have a row of mos devices and would start select by line from the left. It will only select the 1st, 3rd, 5th ...etc. object for odd. The same goes for even objects. Please help.Skill CodeVXLSkill programminglayout XLLayoutSKILL++SelectionSKILL