https://community.cadence.com/cadence_technology_forums/Network with other Cadence users and Cadence technologists...en-USTelligent Community 13https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66326/explorer-menu-disappears-when-switching-simulatorThu, 10 Sep 2026 09:59:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:72967248-0bcf-479a-92ae-6e3b4f42aa9ckkdesboisHello, A custom menu in Explorer, created with deRegUserTriggers , disappears when switching the simulator. Is there any way to prevent that? Laurent.https://community.cadence.com/cadence_technology_forums/system-analysis/f/clarity-3d-solver/66297/join-us-on-wednesday-sep-16th-2026-for-our-next-live-ask-me-anything-session-on-trusting-simulation-clarity-at-50-ghz-and-beyond-and-discover-how-to-achieve-accurate-reliable-results-for-next-generation-high-speed-designs/1409296Thu, 10 Sep 2026 09:36:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:58939b5d-d1fc-4412-8a9b-8dfccdedc901Renu VibhaThank you for your active participation in our past sessions. We hope the discussions were helpful and that we were able to provide timely responses to your questions. As part of our continued commitment to supporting you, our next session is scheduled for September 16 , and we would be delighted to have you join us at 8:30 PM - 9:30 PM IST Topic: Trusting Simulation Clarity at 50 GHz and Beyond .https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66163/automatically-switch-between-sparameter-view-and-rfm-view/1409295Thu, 10 Sep 2026 09:10:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:91ac2a6b-293f-4c8b-a62a-20ee050c18bbamitG22Hi JankoK, Thanks for your response. As I already mentioned in my post, creating separate views with nports and then pointing it to the RFM files may work on a simple test-bench but doesnt work so well in a real transceiver design with multiple passive cells, where each cell has to be extracted over 5 BE corners and at least 3 temperatures. And then imagine creating 15 such cell views with nports pointing to RFM files and 15 cell views with just the EMX spar views. It is a nightmare and just doesn't work. Regarding the RFM file generation, as far as I understood, the quality checking tool doesn't output a rfm file that we can directly use. Regards, Amithttps://community.cadence.com/cadence_technology_forums/orcadx/f/orcad-x-presto-pcb/64674/custom-colour-save/1409294Thu, 10 Sep 2026 08:35:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1fa6f0b5-a114-44e7-a92f-b601b70e6095Ulf KI have not tested the Presto inteface for some time but the last time it was not possible to get the same "skeletal" view in Presto that can be defined in the Allegro for shapes, traces and pads. So for now I am sticking with the classic Allegro PCB Editor.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66325/what-has-been-your-most-challenging-signal-integrity-issue-in-a-recent-design-and-which-sigrity-features-or-workflows-proved-most-valuable-in-diagnosing-and-solving-itThu, 10 Sep 2026 07:18:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:202de8f3-201e-4cb0-b7f7-d47f079c8368Sumithhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66324/how-to-include-exact-0-hz-dc-point-in-powersi-to-avoid-low-frequency-extrapolationThu, 10 Sep 2026 06:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7312cd88-21ce-4983-9677-50b9f7f20079cistheta07Hi Experts, I am currently working on a high-speed PCB design that requires both Power Integrity (PI) impedance profiling and time-domain transient SPICE simulations . My analysis needs to cover the entire frequency range-from static DC up to several gigahertz. When I run standard AC S-parameter extractions in Hybrid Solvers, the solver extrapolates data at low frequencies ( below 100 kHz down to 0 Hz ). As a result, the low-frequency plane resistance ( R_dc ) isn't accurate, which distorts low-frequency die-bump impedance ( Z_die) plots and results in miscalculated bulk decoupling capacitor requirements. Additionally, if I run transient circuit simulations using these extrapolated models, my SPICE solver often experiences convergence issues due to non-physical DC offsets. How can I configure PowerSI to include an exact 0 Hz static DC point in my S-parameter extractions so I don't rely on mathematical extrapolation? Thankyou in advance.Sigrityhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66323/join-our-next-live-ask-me-anything-session-on-system-capture-on-september-23-2026Thu, 10 Sep 2026 05:35:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8baf3208-bf00-4237-97e1-a92674aa7074Renu VibhaJoin us on Wednesday, September 23, 2026 , for our next LIVE Ask Me Anything (AMA) session focused on System Capture . This interactive session offers a unique opportunity to engage directly with experts and ask your questions on System Capture, whether you're looking to deepen your understanding of advanced design methodologies or seeking solutions to everyday design challenges. As always, the discussion will be moderated by a Cadence Engineer , who will share practical insights, best practices, and actionable techniques. Session Details Date: Wednesday, September 23, 2026 Time: 8:30 PM - 9:30 PM IST Location: Join the session here: ( https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66323/join-our-next-live-ask-me-anything-session-on-system-capture-on-september-23-2026 ) Be part of an engaging conversation with fellow engineers and industry experts. We look forward to seeing you herehttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66304/cut-iterations-converge-faster-design-smarter-with-cadence-agentic-ai-join-us-on-16-september-2026/1409291Thu, 10 Sep 2026 05:18:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:779f7c12-13f6-4981-b5ab-3e0a6823d518Renu VibhaHave you registered yet? Don't miss this unique opportunity, Sign up and save your slot. Feel free to forward the invite to your peers, colleagues and customers who you think will be benefitted of this webinar. Look forward to your participation.https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66322/how-to-get-the-top-level-coordinate-of-an-instance-on-lower-levelThu, 10 Sep 2026 03:12:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:23f9d736-c9c4-499b-ba02-b827cd0ff722MartinshThere is a cell named CellX in a hierarchical layout design. The cell CellX is placed on one of lower level of the layout design. How to get the top level coordinate of the bBox of the cell CellX? Thanks!Cadence SKILLLayouthttps://community.cadence.com/cadence_technology_forums/orcadx/f/orcad-x-presto-pcb/64674/custom-colour-save/1409289Wed, 09 Sep 2026 20:52:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:fe2f5a59-acd8-4e6d-b3ae-9397de4ad37bJT20260325479Is this going to be fixed or is this the desired behavior? The whole Presto interface is very impressive but the inability to save and recall layer color assignments is completely unacceptable! The Presto interface is moving forward nicely, but this is a HUGE step backwards even from the Allegro interface! PLEASE FIX THIS!!!!https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66321/using-alternate-schematic-symbolsWed, 09 Sep 2026 19:37:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:50edf9dc-1f3a-4863-ad93-c447a46e9aeaDP202605218058Hi all. I want to replace a schematic symbol on schematic sheet with an alternate schematic symbol that is already assigned to the part. I would think a 'RMB > alternate schematic symbol' would be available, but I don't see anything like that. So how does one choose the alternate schematic symbol to place on a schematic sheet? Again, the alternate schematic symbol is already assigned to the part; I can view it in CIP under the part number, I just can't figure out how to place the alternate on a schematic. OrCAD Capture V22.1https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/66320/improving-fourier-fft-accuracy-in-pspiceWed, 09 Sep 2026 19:12:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:fc7b3afc-1a36-41f2-844a-8efe8426ee8dIshaSIn PSpice, you can often improve the accuracy of your Fourier (spectral) analysis by modifying your transient analysis setup. Accurate Fourier analysis in PSpice depends on selecting appropriate transient simulation settings. The quality of the FFT is directly influenced by the simulation duration, time-step resolution, and overall numerical accuracy. Here are some guidelines for getting more accurate results: _Final Time_ where Tss = Time to reach steady state. The output must reach steady-state before you can even begin to look at the data. Otherwise, the signal is not periodic, and it will introduce noise in the Fourier transform. You can set the No-Print Delay (from the Analysis menu, choose Setup, then click Transient) to Tss to avoid having to restrict the data when using the FFT feature of Probe. Although the simulation still begins at Time=0, No-Print Delay effectively truncates the leading portion of the data file, making it smaller without affecting the accuracy of the FFT. N = Integer number of cycles to be transformed (Frequency domain resolution = F0/N) It is usually best to use 5 or more cycles; the magnitude of the frequency components between harmonics (which should be zero) gives you an idea of what the effective noise-floor of the transform is. F0 = Fundamental frequency In multi-tone analyses, F0 is the highest frequency of which all input frequencies are integer multiples, i.e., F0 = Fi / Ni for all input frequencies Fi, where Ni are arbitrary integers. If you are using the Fourier Analysis function of PSpice, then you should specify the fundamental frequency as F0/N to get the frequency resolution discussed above. _Step Ceiling (and Print Step)_ Nfh = Highest harmonic component with a "significant" amplitude. The Nfh component must be well resolved, at about 25-100 points per cycle (Ntres)."Significant" indicates relative amplitude compared to components to be measured.For example, consider a 1kHz sine wave into a highly nonlinear system. To study the first 5 harmonics, set the Step Ceiling (and Print Step) to 1/(5*1kHz*25)=8us. However, if the accuracy required is 1mV, and one of the neglected higher harmonics is greater than 1mV, then the higher harmonic component can "fold back" (a kind of aliasing) and disrupt the accuracy of the harmonics being measured. 25 This range was derived empirically, but it is interesting to note that if one period of a sine wave is represented by 25 evenly spaced points with linear interpolation, then the maximum possible error is approximately 0.8%,and with 100 points, the maximum error is approximately 0.05%. _Simulation Accuracy_ Simulation accuracy is limited to about 3-3.5 digits (60-70dBc). The accuracy can be improved by tightening tolerances and taking the above considerations to extremes, but not by very much. This may not be considered sufficient for some applications, but keep in mind that even the best simulation models are probably not accurate enough to provide better results. Do share your insights which one from the above helped !!. Happy Learning.pspice advance analysispspice simulationhttps://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66320/explorer-custom-menu-vanishes-when-whanging-simulatorWed, 09 Sep 2026 16:31:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7bb8b131-49dd-4e52-95d5-bca4e672b6a8kkdesboisHello, A custom menu in Explorer, created with deRegUserTriggers , disappears when switching the simulator. Is there any way to prevent that? Maybe, hooking the trigger creation to the event switching the simulator? Laurent.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66296/join-us-on-wednesday-sep-9th-2026-for-our-next-live-ask-me-anything-session-on-allegro-x-pcb-editor-libraries-creation-and-management/1409299Wed, 09 Sep 2026 16:06:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0bc0eb14-b3da-41b3-b8ee-9983327a819emahimagThank you everyone for the great questions and engagement today. Please feel free to share some more topics on which you would like to have these sessions on. Do drop down your topics in the comments below.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66296/join-us-on-wednesday-sep-9th-2026-for-our-next-live-ask-me-anything-session-on-allegro-x-pcb-editor-libraries-creation-and-management/1409298Wed, 09 Sep 2026 16:04:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9e1efdac-b9bf-4d77-8733-43c7a6344089mahimagGreat Question, always make sure that the 3D models are refreshed in the board, if you see warning sign next to the model name in 3DX Model Mapper that indicates there is a need to refresh. Once done, use AUTO to align the step to the symbols. In my opinion, The Auto feature simplifies the initial alignment, but manual adjustments may be required for precise mapping sometimes. So use MAN button to align it to the point.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66296/join-us-on-wednesday-sep-9th-2026-for-our-next-live-ask-me-anything-session-on-allegro-x-pcb-editor-libraries-creation-and-management/1409297Wed, 09 Sep 2026 16:01:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1609cf1f-3523-4ffe-9521-9237998fe974EDAHutI m hopeful this will help. Wil try these going forward. Thank you mahimaghttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66296/join-us-on-wednesday-sep-9th-2026-for-our-next-live-ask-me-anything-session-on-allegro-x-pcb-editor-libraries-creation-and-management/1409296Wed, 09 Sep 2026 15:59:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:899904e8-774f-4263-a343-614d2dc1d1ddmahimagHI EDAHut , I belive you are talking about Allegro Managed Library Solution. The best Practice which I can recommend is that define the roles clearly like Librarian, Designer, Administrator etc. Once Librarian creates and releases the parts,symbols,footprints etc. it will be available to end users from unified search to use in the design. User should request librarian for any updates or changes. I hope this helps!!https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66296/join-us-on-wednesday-sep-9th-2026-for-our-next-live-ask-me-anything-session-on-allegro-x-pcb-editor-libraries-creation-and-management/1409295Wed, 09 Sep 2026 15:49:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d88a1dc5-208d-4f38-9203-c7c79f318fabEDAHutAlso are there any hidden limitations or pro tips when using the automated 3D mapping features in allegro X compared to manually aligning STEP models in older versions?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66296/join-us-on-wednesday-sep-9th-2026-for-our-next-live-ask-me-anything-session-on-allegro-x-pcb-editor-libraries-creation-and-management/1409294Wed, 09 Sep 2026 15:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:beb0ee48-c85d-4646-803d-b3acd2465e64EDAHutHi - Can u pls advise… with allegro x unified library structure. what are the best practices for managing concurrent updates between remote team members without risking database corruption or library overwrites ?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66296/join-us-on-wednesday-sep-9th-2026-for-our-next-live-ask-me-anything-session-on-allegro-x-pcb-editor-libraries-creation-and-management/1409293Wed, 09 Sep 2026 15:27:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:38ceb5ed-9a0d-42e7-8dcc-97cb3268fbdamahimagYes, you can use DesignTrue DFM (Design for Manufacturing) checks here. Before adding DFM constraints, ensure that you define the mask layers in the Cross-Section Editor. Make sure you enable the checks in Setup – Constraints – Modes - Design for Fabri cation > Annular Ring and Design for Assembly– Pastemask Now, create constraint set in CM’s Manufacturing worksheet which can be applied to your design.