https://community.cadence.com/cadence_technology_forums/Network with other Cadence users and Cadence technologists...en-USTelligent Community 12https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66205/unable-to-export-odb/1408995Mon, 27 Jul 2026 17:56:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c76ce108-2bdc-4c07-a923-2f39e69616f2Jeff HDo you have a long path to your .brd file? This is when I typically see this issue. What version of ODB++ INSIDE do you have? The c urrent version, v2604, was just on released April 28, 2026 and it is supposed fix: EBS-178618 — Translation fails for designs on mapped drives with long path names. Resolution: Fixed.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/66206/how-to-remove-an-element-from-a-group-without-deleting-or-disbanding-the-group-using-skillMon, 27 Jul 2026 15:37:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8e4e5e96-e0c1-44b4-a0f9-9107538ce6bcJuanCRLet's say you have a specific group of elements in a brd file and you want to remove one element from this group. How can you remove it without disbanding the group or deleting the element? The SKILL function axlDBRemoveGroupObjects can be used to remove database objects from the specified group. Group members, though removed, are not deleted. axlDBRemoveGroupObjects(o_group lo_members) ⇒ t/nil Arguments: o_group : The database ID of the group from which objects will be removed. o_members : A list of database objects to be removed from the group. A single database ID can be substituted for a list. This function removes the selected objects ( lo_members ) from the specified group ( o_group ). Neither the group nor the member is deleted. The following SKILL code can be used to remove an object from multiple groups at the same time: procedure( removeObjectFromGroup() let((objects_dbid group_dbd group_bibliotec elemnt group) axlSetFindFilter(?enabled list("all") ?onButtons list("noall" "symbols" "shapes")) axlClearSelSet() axlSingleSelectPoint() objects_dbid=axlGetSelSet() group_bibliotec=makeTable("groups" nil) foreach(elemnt objects_dbid foreach(group elemnt->parentGroups if(group then group_bibliotec[group]=append(group_bibliotec[group] list(elemnt))) ) ) foreach(group_dbd group_bibliotec axlDBRemoveGroupObjects(group_dbd group_bibliotec[group_dbd]) ) ) ) Explanation of the SKILL code: The first step in the removeObjectFromGroup() function is to set the Find filter: axlSetFindFilter(?enabled list("noall" "symbols" "shapes") ?onButtons list("noall" "symbols" "shapes")) This will decide what kind of objects you can select on the canvas. In this case, from all possible objects, only “symbols” and “shapes” are selectable; “symbols” and “shapes” are already set to "on". Then, selection of the objects can be done using the following function. Note that there are many functions that let you select objects in different ways. You can read more about it in Allegro SKILL Reference 22.1 > Select and Finds Functions . axlSingleSelectPoint() This function allows you to select a single point on the screen. When this function is called, it will wait for an action from the user to pick a point. Everything that matches the Find filter will be selected. To get all objects selected, use: objects_dbid=axlGetSelSet() The variable objects_dbid can have multiple objects, and each one of these objects can belong to a different group. To classify which object belongs to each group, use a table ( group_bibliotec ): group_bibliotec=makeTable("groups" nil) In the below code, foreach is used to pass by each element of the objects_dbid list. Then, foreach is used again to pass by all parent groups that this element can belong to. The code then checks if the object does belong to any group. If it does, the current element is appended to the group_bibliotec with the matching key. foreach(elemnt objects_dbid foreach(group elemnt->parentGroups if(group then group_bibliotec[group]=append(group_bibliotec[group] list(elemnt))) ) ) To remove the components from the groups: foreach(group_dbd list_groups_dbid axlDBRemoveGroupObjects(group_dbd objects_dbid) )https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66205/unable-to-export-odbMon, 27 Jul 2026 12:19:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0ce44292-9c78-4a92-8853-2d504cb7e877KK202607082958Hello, Vesion 23.1 while exporting ODB++ for a particular board below errors appear. Performed dbdoctor and the brd file doesn;t have any special characters, kindly let me know what could be the issue Thankshttps://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66203/can-t-skip-devices-inside-subckt-in-checks-assertsMon, 27 Jul 2026 12:13:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:74208768-990e-4519-8309-6cf6f6b3383eAD20260518228Hi everyone, I'm having trouble with Checks/Asserts in ADE Explorer and could use some help. What I need: check all bsim4 devices in the bandgap block with abs(vdsat) < 0.3, but skip any devices inside logic cells — for example, an "inv" cell. My setup: · sub = bandgap · primitive = bsim4 · expr = abs(vdsat) < 0.3 · skip_dev_inside_subckt = inv The violating devices in bandgap get flagged fine, but the ones inside the inv cell are not skipped at all. They still show up. I've tried both cell name and instance name for the skip, but it doesn't work. Also, is there a way to highlight the violating devices right on the schematic from the Checks/Asserts results? Would save a lot of time. Any ideas? Thanks.https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66197/how-to-measure-phase-margin-through-deepprobe/1408993Mon, 27 Jul 2026 09:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:47120d0a-7348-4e73-a9b0-d23bd3636f0dAndrew BeckettA small metal resistor is likely to have a very small resistance and unlikely to be significant; given that it's no different from the parasitic resistance of a tiny part of the routing, and you are omitting a small part of that interconnect, even if you include the parasitics from extraction you wouldn't be missing much... Andrewhttps://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66197/how-to-measure-phase-margin-through-deepprobe/1408992Mon, 27 Jul 2026 08:15:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:5a990fe2-b79a-4dd2-b885-4bc622db7cf8VIRAJ PANCHALThank you Andrew, now it worked. your article has information regarding this thread. Thank you.https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66197/how-to-measure-phase-margin-through-deepprobe/1408991Mon, 27 Jul 2026 08:14:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ac01c9b5-e4de-4d36-9626-006ffce3d4e0VIRAJ PANCHALThank you for your suggestion and respond, now it worked. I've another little doubt then, if we ignore the resistance while doing simulation then why do we keep the resistance in feedback path.? Thank you.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66201/script-file-to-convert-max-file-to-brd/1408990Mon, 27 Jul 2026 06:41:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:147678b7-25a5-44f0-b7dc-aed5d380c7a9vidhyaparameswariHi Siri, Please note that the OrCAD to Allegro Layout Translator is no longer supported on current releases, as it is not compatible with 64-bit platforms. As a supported migration workflow, OrCAD Layout .MAX design files can first be translated into an OrCAD 16.6 (.brd) database. The translated design should then be opened and saved in OrCAD 17.2 or 17.4 (.brd) format before being migrated to later versions . For users who have access to a version 16.6 that still contains the OrCAD Layout translator, the translator may be hidden by default. To enable it: Open Setup → User Preferences . Navigate to the Unsupported section. Enable the variable layout2allegro_unsupported . Restart Allegro PCB Editor . After restarting, the translator should be available under: File → Import → CAD Translators → OrCAD Layout This utility can be used to convert an OrCAD Layout .MAX design file (for example, version 15.7) to the Allegro .BRD format.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66194/join-us-for-our-next-live-experts-session-powersi-s-parameter-analysis-on-july-29th-2026/1408989Mon, 27 Jul 2026 06:06:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f9adc6fd-a7b8-41d8-9692-ff58c9d6d2f4Renu Vibha2 days to go! Don't miss this opportunity to engage and discover proven approaches to your SI challenges. Join us on Wednesday July 29th at 8:30-9:30PM ISThttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66201/script-file-to-convert-max-file-to-brdMon, 27 Jul 2026 05:33:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:75c6afd5-c327-462d-b339-c1fe047d18c7SiriHello, Could you please let us know if there is any available script or utility to convert an 15.7 .MAX design file to the .BRD format? Thankshttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66200/donut-padMon, 27 Jul 2026 01:59:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:546107a5-c246-422b-8082-ad7fd34bb4b0MM202607263411Hello, I'm a bit confused bout the difference between donut pad and plated thru pin. And why does some donut pads has paste mask. Can you help me with clear these? Thank you!https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/51981/donut-pad-with-allegro-padstack-editor/1408988Mon, 27 Jul 2026 01:55:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:63a314f9-acd0-4904-9816-ee95a19251e3MM202607263411Hello, What's the difference between the plated thru pin and donut pad? Thanks in advance!https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66199/hi-how-to-hide-a-set-of-parameter-section-in-pcell-generation-using-pcdefinepcell-fuction/1408987Sun, 26 Jul 2026 19:40:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6f9e3d47-57a7-43db-9b1e-3ba8b48e20a9Andrew BeckettYou need to define CDF for the cell; then you can control the editable and display callbacks to control whether a particular parameter is displayed or not. Andrewhttps://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66199/hi-how-to-hide-a-set-of-parameter-section-in-pcell-generation-using-pcdefinepcell-fuctionSun, 26 Jul 2026 17:44:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:24f5e97d-9c4c-4773-940d-16bf19171bfcGanesh BHi, How to hide a set of parameter section in pcell generation using "pcDefinePCell()" fuction. Can anyone help? Just like this.https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66197/how-to-measure-phase-margin-through-deepprobe/1408986Sun, 26 Jul 2026 13:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:cc50ebc5-8a98-4671-9ae9-9b60652b71f9Andrew BeckettI agree - this is covered in my article How to perform a stability (stb) analysis on a loop within an extracted view or DSPF file Andrewhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66198/spacemousen-3d-mouse-supportSat, 25 Jul 2026 23:15:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8ccdd827-a434-486c-9185-8ee3918e2c96JH202606267441Has it been brought up that support for the 3D Connexion SpaceMouse would be really helpful for panning, rotating, and zooming both 2D and 3D UI. Please add support for using the SpaceMouse.https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66197/how-to-measure-phase-margin-through-deepprobe/1408985Sat, 25 Jul 2026 22:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b7908fdc-1532-4611-9fa9-b9bac9f762c9ULPAnalogI do not see what IPRB3 is in the figure posted. Generally, how I would approach this is by placing a small metal resistor in the circuit where you would have normally inserted iprobe. Then, in config view, I would bind the metal resistor to open. In the testbench I would create two instances of deep probe that are setup to probe either side of the metal resistor and connect them across an iprobe. This is the probe that would be specified in stb analysis. Alternatively, you could specify the instance terminal instead of adding an iprobe. I am assuming that your pdk has metal resistors.https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66197/how-to-measure-phase-margin-through-deepprobeSat, 25 Jul 2026 15:38:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:64ce8a06-6bf0-4e82-abc9-445341cb5424VIRAJ PANCHALHello community, I am doing the verification of one block. I want to measure the phase margin(PM) though stability analysis. I know the method to measure the phase(i.e connect iprobe in feedback path). But my this circuit is complex, so I want to measure the PM from top level testbench so I am using the deepprobe and cds_thru to connect the signal. but I am unable to measure PM. In maestro view I got error message in PM expression. So my question is that is this a right method to measure PM. if it is right then which probe should I select in stability form.?ADE ExplorermaestroAnalysisVirtuosoSpectresimulationhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66166/opening-project-done-in-cadence-16-6-with-free-version-25-1/1408983Fri, 24 Jul 2026 19:56:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:151363ea-d04f-47ad-b09d-7dd301291477VA202606266120Good day @Zhifeng Jin. Thank you for your answer. I have been trying to open it with the system capture viewer (which comes with the free trial version), but in this version there is no possibility for "Project from Existing Design". I have suscribe for a free trial of the system capture (for Allegro X free trial request ( Allegro X Free Trial | Cadence )), but havng gotten any reply yet. I will wait for this and come back.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66166/opening-project-done-in-cadence-16-6-with-free-version-25-1/1408982Fri, 24 Jul 2026 19:49:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:680cda9c-c12a-46e9-a58b-266e5f4d6804VA202606266120Hello @Elecguy . Yes, I tryed dbdoctor, from which I could see the PCB board, but not the Schematic. As I have seen/read, its because the version in which it was created.