https://community.cadence.com/cadence_technology_forums/Network with other Cadence users and Cadence technologists...en-USTelligent Community 13https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66275/how-can-a-concatenated-string-be-transformed-into-a-variable-name/1409212Fri, 21 Aug 2026 05:10:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:aa36279a-a35f-44b3-b992-91f3c3e61c9aSZ20260803361Source code is shown below load_form.il: (let (load_en reload_en) procedure(load_form() cond( (dock_W load_en = nil reload_en = t ) (t load_en = t reload_en = nil ) ) layoutForm_pte~>loadpte_button~>enabled = load_en layoutForm_pte~>reloadpte_button~>enabled = reload_en hiDisplayForm('layoutForm_pte) ) ) load_procedure.il: (let (a b ns) procedure(loadpte(a) load("test_layout_demand.il") hiFormClose(a) layoutForm_pte~>loadpte_button~>enabled = nil layoutForm_pte~>reloadpte_button~>enabled = t ) procedure(reloadpte(a) b=hiDockWindow( ?window dock_W ) if(b==t then hiFormClose(a) else dock_W=hiCreateDockWindow( ?appType "layout" ?widgetType "form" ?form appForm ) ns=hiGetWindowList('session) foreach( n ns hiDockWindow( ?window dock_W ?session n ) ) ) ) ) gui_contain.il: (let (load_en reload_en loadpte_button reloadpte_button loadpte reloadpte boxLayout_ver ) dock_W = nil load_en = t reload_en = nil loadpte_button = hiCreateButton( ?name 'loadpte_button ?buttonText "Press this button for initial loading:" ?callback "loadpte(layoutForm_pte)" ?enabled load_en ) reloadpte_button = hiCreateButton( ?name 'reloadpte_button ?buttonText "Click to Reload: " ?callback "reloadpte(layoutForm_pte)" ?enabled reload_en ) boxLayout_ver = hiCreateVerticalBoxLayout( 'boxLayout_ver ?items list(loadpte_button reloadpte_button) ) layoutForm_pte = hiCreateLayoutForm( 'layoutForm_pte "LOAD PTE" boxLayout_ver ) ) test_layout_demand.il: (let (addMosW_string addMosW_button gridLayout boxLayout loadpte_button reloadpte_button boxLayout_ver ns) addMosW_string = hiCreateStringField( ?name 'addMosW_string ?prompt "M1_width: " ?defValue "1.5" ) addMosW_button = hiCreateButton( ?name 'addMosW_button ?buttonText "apply" ?callback "(AddMosM1)" ) gridLayout = hiCreateGridLayout( 'gridLayout ?items (list list( addMosW_string 'row 0 'col 0 ) list( addMosW_button 'row 0 'col 1 ) list( 'col_stretch 0 1) list( 'col_stretch 1 0) ) ) boxLayout = hiCreateHorizontalBoxLayout( 'boxLayout ?items list(gridLayout) ) appForm = hiCreateLayoutForm( 'appForm "LAYOUT_PTE" boxLayout ) procedure(AddMosM1() let((cv objs metal1 temp temp1 shapes x y ux uy xy row column transform M1_width) M1_width = evalstring(appForm~>addMosW_string~>value) cv = geGetEditCellView() objs = geGetSelSet() foreach(obj objs transform = nil if(obj~>objType == "inst" then transform = list(obj~>transform));end if if(obj~>objType == "mosaic" then x = xCoord(obj~>xy) y = yCoord(obj~>xy) ux = obj~>uX uy = obj~>uY row = obj~>rows column = obj~>columns for(a 0 row-1 for(b 0 column-1 case(car(obj~>tileArray) ("R0" || "MXR90" xy = list(x+a*ux : y+b*uy)) ("R90" || "MY" xy = list(x-a*ux : y+b*uy)) ("R0" || "MXR90" xy = list(x+a*ux : y-b*uy)) ("R0" || "MXR90" xy = list(x-a*ux : y-b*uy)) );end case transform = append1(transform list(car(xy) car(obj~>tileArray) 1.0)) );end for );enf for );end if shapes = obj~>master~>shapes foreach(shape shapes if(car(shape~>lpp) == "M1" && cadr(shape~>lpp) == "drawing" then foreach(trans transform metal1 = dbCopyFig(shape cv trans) temp = leConvertPolygonToPath(metal1) temp~>width = M1_width );foreach );if );foreach );foreach );let );proc dock_W=hiCreateDockWindow( ?appType "layout" ?widgetType "form" ?form appForm ) ns=hiGetWindowList('session) foreach( n ns hiDockWindow( ?window dock_W ?session n ) ) )https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66275/how-can-a-concatenated-string-be-transformed-into-a-variable-name/1409211Fri, 21 Aug 2026 04:20:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e54710bb-d8df-4cd7-ba5b-b9e3bb184c64SZ20260803361This project is developed to meet requirements from the layout team. They need a persistently‑pinned UI panel that can be activated by clicks at any time. For this purpose, I planned to use dockWindow so that the panel can be docked inside the PTE frame. However, I have run into multiple issues during development, as listed below: With my current implementation, the dock window is only created for a single session window. My expectation is to make this dock window available for multiple session windows simultaneously. How can I completely delete an appForm from memory? I create an appForm via hiCreateLayoutForm, then construct the dock window with: dock_W = hiCreateDockWindow( ?appType "layout" ?widgetType "form" ?form appForm ) Afterwards I render the dock window with: foreach( n ns hiDockWindow( ?window dock_W ?session n ) ) My intention is to automatically unset the global variable appForm after the dock window is generated. When creating the dock window for another session window, I would recreate the global appForm variable. If fully destroying appForm is not feasible, I considered generating time‑dependent unique variable names. Each time a new session window opens, a brand‑new global variable such as appForm_currentTime would be generated to avoid naming conflicts caused by re‑using the same variable appForm. This is the motivation behind my post. There are three global variables in my codebase: appForm, layoutForm_pte and dock_W.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66277/how-to-create-a-schematic-symbol-for-an-existing-custom-footprint-padstacks-already-built-in-allegro-x-25Fri, 21 Aug 2026 02:38:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:5563b314-aab1-43a3-b35f-0be4f7658a14AT202608047036Hey, I've already built the padstacks and copper layout for a custom part (an inverted-F antenna element) as a footprint in the PCB library. Now I need to create the matching schematic symbol so I can place it on my schematic page and have it map to that existing footprint. What I've checked so far: File > New only offers Project, Block, Footprint, and Template based footprint — there's no "Symbol" option. Place menu has Component, Wire, Bus, Special Symbols, Schematic Block, Abstract Component, etc. — nothing for creating a brand-new symbol from scratch. Tools menu has Generate BOM, Launch PCB Editor, Cadence Unified Library Generator, and Part Manager. I tried a few menus but none worked for me. Any help is appreciated.https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66275/how-can-a-concatenated-string-be-transformed-into-a-variable-name/1409210Fri, 21 Aug 2026 02:32:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:710d6211-9b69-4563-9f9e-6d87266beb06SZ20260803361Dear Mr. Beckett, Thank you very much for your prompt, professional and informative replies. I have tried both of your proposed methods, and both work as I expected. I will test the hash‑table approach you suggested later. I will elaborate on why I require dynamic variable names based on a small ongoing project I am developing, and seek your advice on the issues I have encountered during development. Best regards, Stevehttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66254/what-is-preventing-designers-from-improving-decoupling/1409209Thu, 20 Aug 2026 22:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e5346683-0d0a-4004-b441-93dafe4a2377John THi Avant, yes this rings a bell with me too having previously designed for high volume production also. Does anyone ever pre-plan placement to account for smd side1 versus smd side2 assembly? One neat trick we came up with was placing vias in pad for components placed on the smd 2 side. Side 1 being already pasted and soldered; any paste that might come through due to the side 2 soldering will then not cause any interference with production of the opposite side, such as no stencil lifting. Would be interested to hear any other thoughts or tricks!https://community.cadence.com/cadence_technology_forums/orcadx/f/orcad-x-presto-pcb/66276/drc-exceptions-not-honored/1409208Thu, 20 Aug 2026 17:41:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9b672940-b5ea-4bd5-8c6c-fff1590780d5rg13A Capture design cannot have parts that have visible pins with duplicate pin names. Only invisible power pins can have the same name, and they all connect to the same signal. If you have Cadence ASK portal access, then you can refer following: Article (20451812) Title: Getting ERROR (ORCAP-36041) for duplicate pin name while creating netlist for Allegro PCB Editor URL: https://ask.cadence.com/ASK/article-viewer?id=a1Od00000066QHbEAM&pageName=article-viewerhttps://community.cadence.com/cadence_technology_forums/orcadx/f/orcad-x-presto-pcb/66276/drc-exceptions-not-honoredThu, 20 Aug 2026 17:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:be29dbd6-ea8e-4cfa-b080-785737221013passedpawnI want to allow duplicate pin names. I get the error ORCAP-36041 when I do this, so I don't want errors for this. Adding this error to the DRC>Exception Setup list does nothing - the error still occurs and I cannot generate a netlist. What am I doing wrong?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66254/what-is-preventing-designers-from-improving-decoupling/1409206Thu, 20 Aug 2026 14:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b375ed43-38ad-42cf-8412-269b489402a2avantWe don't use via-in-pad. We produce 1M+ units a year. Expense and manufacturing issues outweigh benefit for us. We typically use #2 with vias tied to planes, and wide traces. We use a lot of 0201 decoupling caps.https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66275/how-can-a-concatenated-string-be-transformed-into-a-variable-name/1409204Thu, 20 Aug 2026 12:03:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3e7cb5b6-6d33-4ca4-a1ef-b5ffc3d5c598Andrew BeckettThis is almost certainly not what you want to do, because creating different variable names on the fly usually means you should be creating a different data structure - e.g. a hash table indexed by the date rather than a unique variable name. However, if you really want to do this (the wrong way in my opinion), then taking your code: item="" lists=setof(i parseString(getCurrentTime() "") i!=" " && i!=":") foreach(elem lists item=strcat(item elem) ) (I assume you used some kind of optical character recognition because it had some spurious parentheses) then you could do: set(concat("a_" item) 5) you can retrieve it with: symeval(concat("a_" item)) A cleaner (more efficient in terms of creating garbage that needs collecting) way of building the variable name would be to do: cleanup=pcreCompile("[ :]") varName=concat("a_" pcreReplace(cleanup getCurrentTime() "" 0)) However, if you creating a number of these, I'd use a hash table (using makeTable) as I mentioned before. Regards, Andrewhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/64632/how-to-install-allegro-free-physical-viewer-16-6/1409203Thu, 20 Aug 2026 10:53:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6e8b03b0-e705-49c0-a421-fc142155ab8bTT202608201024Hi, I also need Allegro Free Physical Viewer 16.6 or 17.4 to open a legacy BRD file saved in version 16.6. The current Allegro X Free Viewer shows error SPMHDB-181 and cannot open the file. Could you please share the installer or download link with me by email? Thank you.https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66275/how-can-a-concatenated-string-be-transformed-into-a-variable-nameThu, 20 Aug 2026 09:07:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:4b349ab0-addb-4d80-b813-fb0ace26d583SZ20260803361I want to set a variable name that can change over time. For example: item="" lists=setof(i parseString(getCurrentTime() "") i!) =" "&&i! =":") foreach(elem lists item=strcat(item elem) ) I received the item with the code "Aug201706212026". I want to replace the "item" in the variable name "a_item" with "Aug201706212026", so that the final variable name becomes "a_Aug201706212026". How can I do this? I tried using `setq(stringToSymbol(strcat("a_" item)) 5)`, but this caused an error. How should I proceed?Cadence SKILLSkill programmingVirtuosoSKILLhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409202Wed, 19 Aug 2026 15:11:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b65d951c-cf16-4b48-aad1-bcc7f34375b7AK20250609765Thank you everyone for the great questions and engagement today. We will follow up on pending items shortly and appreciate your participation.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409201Wed, 19 Aug 2026 15:09:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0e9c3eb9-7a7c-46f9-869c-49c34baecb0cAK20250609765Thank you for the question. When a channel fails compliance testing, engineers typically investigate insertion loss, return loss, crosstalk, ISI, eye margin, and SNR . The goal is to determine whether the failure is caused by excessive channel attenuation, reflections from impedance discontinuities, coupling from aggressor nets, or degraded receiver margin. In practice, S21 (insertion loss), S11 (return loss), crosstalk, eye opening, and SNR are among the most important indicators used to isolate the root cause of a compliance failure.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409200Wed, 19 Aug 2026 15:04:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ee33efa8-428c-4fae-9f25-2d1af16a5106AK20250609765The handoff typically breaks down when the logical connectivity used during topology creation no longer matches the physical implementation. Pin-name mismatches, component-definition differences, or connectivity mapping issues can prevent correct constraint transfer, forcing manual re-assignment of routing constraints in the layout flow. Maintaining consistent schematic-to-layout mapping is key.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409199Wed, 19 Aug 2026 14:57:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d0ddd603-c619-4211-aab8-ecf7b4afffcdCF202606104231When a channel fails compliance testing , what SI metrics is typically investigated?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409198Wed, 19 Aug 2026 14:54:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0c947733-3416-433c-8979-a4361943e9d2EDAHutDuring pre layout engineer creates a tuned LPDDR4 memory topology with specific termination resistors using generic schematic nodes … when transferring this to physical layout , mismatching pin names between the schematic symbols and the actual layout footprints break the net connectivity mapping in Aurora .. this completely resets the constraint manager rules, forcing the layout team to manually reassign routing constraints from scratchhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409197Wed, 19 Aug 2026 14:54:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6295edff-319d-4be9-ba90-a3c95a56af03AK20250609765Thank you for the question. AI servers and high-performance computing (HPC) systems introduce several unique challenges for signal integrity (SI) engineers: Heterogeneous Architectures: The integration of various processing units, such as CPUs, GPUs, and AI processors, requires careful management of signal integrity across different components, which can complicate design and validation processes. High-Speed Signaling: The demand for high-speed data transfer increases the risk of signal integrity issues, including crosstalk, attenuation, and reflections. Engineers must implement advanced techniques to mitigate these effects. Memory Bandwidth Limitations: The "memory wall" phenomenon, where memory bandwidth does not scale with the number of cores, poses challenges in ensuring that data can be efficiently accessed and processed without bottlenecks. Thermal Management: Increased power consumption from high-performance components generates heat, which can affect signal integrity. Engineers must design effective cooling solutions to maintain optimal operating conditions. Electromagnetic Interference (EMI): The complexity of modern AI workloads can lead to increased EMI, necessitating careful design to minimize interference and ensure compliance with regulatory standards. Complex Routing Constraints: The intricate layouts required for high-speed signals on PCBs can lead to routing challenges, requiring innovative design strategies to maintain signal integrity. Modular Designs: The shift towards disaggregated architectures and modular designs, facilitated by standards like UCIe, requires SI engineers to adapt to new connectivity standards and ensure compatibility across diverse components. Addressing these challenges is crucial for the successful deployment of AI servers and HPC systems, ensuring reliable performance and efficiency in demanding environments.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409196Wed, 19 Aug 2026 14:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:892361ba-5118-4e08-aaa2-d4fc91ffd8ecAK20250609765Thank you for the question. Before running detailed SI simulations, I would recommend using the PowerSI ERC - Trace Imp/Cpl/Ref Check workflow. While impedance may be within specification, SI issues can still arise from excessive coupling, missing or discontinuous reference planes, and localized routing violations . The ERC workflow automatically checks these conditions and reports violations through detailed tables and layout overlays, making it easy to identify the exact trace segments responsible for potential SI degradation. This allows layout issues to be corrected early, reducing simulation iterations and improving overall design quality.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409195Wed, 19 Aug 2026 14:45:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:71b09034-6a20-44ab-a1ee-7f62d2e8b257cistheta07In a high-speed DDR or SerDes design, impedance may be within specification, yet signal integrity issues can still occur. What layout-related factors should be investigated to identify the root cause before running detailed simulations?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409194Wed, 19 Aug 2026 14:44:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f58cc4e8-2371-41c9-8209-de9b1e514402EDAHutWhere does the handoff from schematic driven topologies to physical layout in Cadence Sigrity Aurora break down the most ?