https://community.cadence.com/cadence_technology_forums/Network with other Cadence users and Cadence technologists...en-USTelligent Community 12https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66130/don-t-miss-our-live-interactive-upcoming-orcad-x-session-on-july-8th-wednesdayThu, 02 Jul 2026 14:36:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:30a2e6ab-46a3-43dc-a840-65ccc8980d57Renu VibhaCurious about what other users are trying in latest release of OrCAD X—or looking to solve design challenges faster? Join our live, interactive session with Cadence experts and get real-time answers to your toughest PCB design questions. Date : July 8, 2026 at 7:30 – 8:30 PM IST Location : here What’s on the agenda: Cloud Features: Work in shared cloud workspaces, create and manage components, track revisions, control versions of design and collaborate seamlessly. Variants: Create BOM Variants, manage alternate and substitute parts, and export variant.lst file for downstream manufacturing processes. Why you should attend: Get instant answers to your questions See real-world use cases in action Connect and exchange insights with peers Bring your challenges, explore new possibilities, and walk away with actionable insights. Save your spot now and be part of the conversation, register now !https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66124/how-to-run-an-interactive-external-script-from-skill/1408831Thu, 02 Jul 2026 13:36:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:13eeba65-0ca0-4404-809e-42697a7c113fAndrew BeckettYou are not allowed to republish content from the ASK portal (so for that reason, I removed it). You should be able to log in - if you are having trouble, follow the link on the login page Cadence ASK Help .https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66124/how-to-run-an-interactive-external-script-from-skill/1408830Thu, 02 Jul 2026 13:24:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e319de1f-9b0b-4f28-a0f5-309419c42040JY20260624860Here is the sample code from the linked page: Interfacing between Shell, Perl, Tcl, and Python commands in Virtuoso Content Removed by Moderatorhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66115/fanout-of-outer-layer-gnd-smd-pins-to-via-in-pad-in-allegro/1408829Thu, 02 Jul 2026 13:01:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ab284414-6d53-4550-a065-1576b5fe9c20HoangkhoipcbHi BC202603263145 , You can try following this suggestion. It runs on the version OrCAD X PCB Professional Plus 25.1 BR, HoangKhoihttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/66129/how-to-import-a-techfile-through-skillThu, 02 Jul 2026 12:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:724bfde6-78c7-4dad-b6b3-f16d0f02e3c6JuanCRaxlRunBatchDBProgram can be used to import a techfile. Open the design in Allegro X PCB Editor or Package Designer and type skill at the command line: Command > skill The command line changes to the Skill prompt: Skill > The following skill code will create a log file and import a techfile. In the following skill code, replace mytechfile.tcfx with your own techfile name including the .tcfx extension: Skill > axlRunBatchDBProgram("techfile" "techfile -$ -r mytechfile.tcfx %s" ?reloadDB t ?logfile "techfile") Wait while the techfile (apd) runs: The view of the techfile UI will appear. Scroll to view the summary. Close the file. In the database, to exit from the skill prompt, type exit : Skill > exit The Command window changes from Skill > to Command > : Command >https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66124/how-to-run-an-interactive-external-script-from-skill/1408828Thu, 02 Jul 2026 11:33:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:00ac7b88-9d24-425a-992d-ae6005b69e09LoVyacheslavvVEMsThank you very much for your reply! Unfortunately, due to circumstances beyond my control, I'm currently unable to authenticate, so I can't access the solution you linked. Would it be possible for you to post the solution here? It would really help me, and I think it could also be useful for other people who come across this thread in the future. Thank you in advance!https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66128/ade-explorer-how-to-pass-a-design-variable-to-a-parameter-array-and-another-design-variable-as-a-string-parameter-to-an-instance---spectre-vs-amsThu, 02 Jul 2026 10:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:92b253aa-bef5-4cb2-aadc-4b3060c88af8Volker THi, I am referring to the following two blog posts, both dealing with ADE Explorer and/or Spectre, as an introduction to a similar problem I have with ADE Explorer and AMS. ADE Explorer and Spectre 1. How to Pass a String Design Parameter to a Cell 2. Defining Verilog-A vector in the maestro view The first deals with the issue that when we have a parameterizable cell, like e.g. an instance "myInstance" of a cell using a Verilog-A view, that has a string parameter, e.g. " fname " that we want to specify by design variable, the Spectre netlist does not contain the value of the design variable, but its name only. Example: At the beginning of the Spectre netlist, we see the parameters passed to Spectre, e.g. parameters temperature=27 vdd50=5 fname="/tmp/mylogfile.log" \ debuglevel=1 tperiod=50n trise=100p tsdelay=10n But later in the netlist, when we look at the instance "myInstance" that receives some of these parameters, one of which is the " fname " string parameter, we only see myInstance trise=trise tfall=trise tdelay=0 \ tsdelay=tsdelay tperiod=tperiod vdd=vdd50 logfile=" fname " So, instead of our string defined by design variable value, we only see the design variable name as a string passed to the instance's string parameter " logfile ", The solution shown by Andrew Beckett suggests to use SKILL functions to remove the respective string parameter while leaving the other string parameters in place: almGetStringParameterList("mylib" "mycell" ?view "veriloga") => (fname someOtherParam somethingElse) almSetStringParameterList("mylib" "mycell" '(someOtherParam somethingElse) ?view "veriloga") => (someOtherParam somethingElse) The former function identifies all string parameters used by the respective view of a cell of a library ( fname , someOtherParam and somethingElse in the example shown) and then the latter function can be used to set the same list minus the string parameter we would like to pass by design variable (e.g. fname ) as the new string parameter list. That way, our Spectre netlist gets the value of the string parameter, and not only its name. Now the beginning of the Spectre netlist still looks like this: parameters temperature=27 vdd50=5 fname="/tmp/mylogfile.log" \ debuglevel=1 tperiod=50n trise=100p tsdelay=10n But later in the netlist, when we look at the instance "myInstance" that receives some of these parameters, one of which is the "fname" string parameter, we now see myInstance trise=trise tfall=trise tdelay=0 \ tsdelay=tsdelay tperiod=tperiod vdd=vdd50 logfile= fname So, instead of "fname" (in quotes, hence being a string), we only see fname without quotes, hence referencing the respective Spectre parameter. Problem solved, instance parameter " logfile " is now fed by Spectre parameter " fname " containing string value " /tmp/mylogfile.log " of design variable " fname ".. -- The second post deals with parameter arrays. Again, let's assume we use an instance of a cell using a Verilog-A view, that has a parameter array, like parameter integer pattern[2:0] = {1, 2, 3}; and we would like to use a design variable " myPattern " for the definition of the pattern, in ADE, then we cannot just enter [4 5 6] for that design variable value to define a new pattern, as ADE interprets that as a literal or SKILL code. Andrew Beckett shows the solution for this in the referenced post #2, namely to use strcat("[4 5 6]") as design variable value instead. This gives valid SKILL code for ADE, translates into string "[4 5 6]" , which translates into Spectre parameter [4 5 6] . Example: At the beginning of the Spectre netlist, the parameter list now is parameters myPattern=[4 5 6] vdd50=5 fname="/tmp/mylogfile.log" \ debuglevel=1 tperiod=50n trise=100p tsdelay=10n Later, when the respective instance occurs in the netlist, we see something like myInstance trise=trise tfall=trise tdelay=0 pattern=myPattern \ tsdelay=tsdelay tperiod=tperiod vdd=vdd50 logfile=fname So, similar to the string parameter described before, the instance parameter now gets assigned the correct Spectre parameter. So far, so good, problems solved for ADE Explorer and Spectre. ADE Explorer and AMS Now let's use the same test bench, using the same cells and design parameters, but AMS as a simulator. As far as I know, AMS uses a different netlister (UNL?), and that apparently behaves differently. The instance now gets its parameters assigned like this myInstance #(.trise(cds_globals.trise), .pattern("myPattern") .tperiod(cds_globals.tperiod), .tsdelay(cds_globals.tsdelay), .vdd(cds_globals.vdd50), .tdelay(0), .tfall(cds_globals.trise), .logfile("fname") , .debuglevel(cds_globals.debuglevel)) I1 (.nrst( nreset ), .mclk( mclk ), ... ); There is no "pre-translation" of design variables into AMS parameters to be found as a list (but apparently there exists one, named " cds_globals ", as one can see for the other parameters). But both the string parameter and the array parameter do not show up in cds_globals but are used directly as a string containing the design variable name instead of its value. So the question is, is there any trick similar to the two shown for Spectre that we can create a netlist using design variable values instead of design variable names?https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66116/efficient-iterative-methods-for-threshold-extraction-ex-extraction-of-the-input-referred-offset-voltage-of-a-clocked-comparator-or-the-calibration-code-of-a-bandgap-etc/1408827Thu, 02 Jul 2026 07:35:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0aefc68f-2b3c-4dbc-8e12-1b95fcf94291AVAQ SemiA practical way to solve this is to treat the problem as a root-finding/search problem rather than a brute-force sweep. For quantities such as comparator input-referred offset, bandgap trim code, LDO trim code, or any calibration parameter where the output changes monotonically with the search variable, a binary search (successive approximation) is usually the most efficient approach. Instead of sweeping hundreds or thousands of values, each simulation halves the remaining search range, so the number of iterations grows as log₂(N) rather than N . This provides a dramatic reduction in simulation time while maintaining the desired resolution. In Cadence/Spectre, I've had good results implementing this using either: SpectreMDL with looping/search statements. SKILL/OCEAN scripts that automatically update the design variable after each simulation. A small Verilog-A controller that performs the search internally, which is especially convenient for Monte Carlo characterization. For clocked comparators, I also recommend combining the search algorithm with Monte Carlo mismatch so that each sample converges to its own offset voltage automatically, instead of performing a dense input sweep for every run. This is significantly faster than the traditional ramp-based method while producing essentially the same statistical results. The key requirement is that the calibration variable has a monotonic relationship with the measured metric. If hysteresis or multiple stable operating points exist, the search algorithm should be modified accordingly (for example, by defining separate rising/falling thresholds or using a hysteresis-aware search strategy).https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/66107/axldesignflip/1408826Thu, 02 Jul 2026 06:37:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ba18769f-eaff-4392-a6b8-d0f7efc925ccDavidAhlI got confirmation from our support that it is a bug in 25.1. They have created a case with Cadence to get it fixed.https://community.cadence.com/cadence_technology_forums/system-analysis/f/clarity-3d-solver/66127/setting-up-and-simulating-rigid-flex-designs-in-powersi-from-odb-importsThu, 02 Jul 2026 06:36:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e25c448c-5c3f-4647-90b4-111d2d58efffALLpdfThe most robust and recommended approach is ODB++ > Allegro > PowerSI Workflow . Steps: Import the ODB++ file into Allegro . Verify and configure: Rigid‑Flex zones Stackups for rigid and flex regions Save the design as an Allegro .brd file . Import the .brd file into PowerSI for simulation. This workflow (ODB++ > .brd > .spd) is considered more stable and reliable especially for complex Rigid‑Flex designs.https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66126/innovus-with-variable-metal-width-based-on-metal-lengthThu, 02 Jul 2026 05:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c6aa7378-c145-4903-a612-b12734fdea5eVictorPengHi, I was tring to use Innovus to do PnR, and I am facing the problem that I have to widen the metal wires if their lengths excess a certain limit, for example, a M1 100um metal needs to be widened to 1.5um from the default 0.5um width. I did not find any techlef constrains that could do it or I might miss it. I know that I could setup NDRs in Innovus and route with a wider metal but I just want the metal shapes that excess the limit to be widened not the entire net. Are there any suggestions other than NDRs? Thank you!routePnRInnovushttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66123/disable-cm-updates-or-audits-during-component-replace-through-tcl/1408824Wed, 01 Jul 2026 14:19:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e286fb08-0310-4d59-8264-39d2d0d9e8b7PatEscherI would need to confirm this with our client, but I am pretty sure that Constraint manager is enabled. Cadence Version is SPB 23.1https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66123/disable-cm-updates-or-audits-during-component-replace-through-tcl/1408823Wed, 01 Jul 2026 12:46:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:727cbdef-9344-4b5f-a1b1-3f15b511afb9TechnoBobbyHi PatEscher , Just to narrow this down, these connectivity updates are typically triggered when Constraint Manager is active in Capture. Could you please confirm if Constraint Manager is enabled from Schematic Capture in your setup and whether you are actively using it in this design? Also, it would be helpful to know which Capture version you are currently using. These CM push and ECSet audit messages are generally observed only when Constraint Manager integration is enabled, so this information will help in understanding the behavior more accurately.https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66124/how-to-run-an-interactive-external-script-from-skill/1408822Wed, 01 Jul 2026 12:33:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3893c33f-0da4-4483-b377-ddfccec5e3f1RobManInterfacing between Shell, Perl, Tcl, and Python commands in Virtuosohttps://community.cadence.com/cadence_technology_forums/computational-fluid-dynamics/f/pointwise/66125/unstable-connection-to-active-glyph-serverWed, 01 Jul 2026 12:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:71455c87-a6f1-4238-9b1d-60bf73a03ac6RF20260309933Hi All, For a project I am looking to implement an automated meshing pipeline using the python API. I am running into issues with the stability of the connection to my localhost. The Pointwise GUI is running as instructed (active glyph server with default port 2807). The license is also correctly reserved as I can use the GUI as intended. The issue I am encountering is that my test scripts connect to Pointwise unreliably. For example, I ran the provide backstep python example program as provided on github ( https://github.com/pointwise/GlyphClientPython/blob/master/examples/BackstepTutorial.py ). It worked as expected last evening, but this morning I get the attached error message in my console: Both the test code and the provided Backstep Tutorial have ran without issue on my machine. In quick succession as well and multiple times. When the error occurs, I get the response that the server is busy. Note that I have tried restarting my PC, it does not help. Have any of you encountered this problem before, and how was it resolved? Is there a way to check and terminate active server connections in the pointwise GUI? Any other tips or tricks? See also the exact code I use attached. The extension is .txt, as .py is not allowed on this forum. Note that the test program is less then 10 lines of code. Thanks in advance for your assistence, Kind regards, Roelof Fennema community.cadence.com/.../PW_5F00_Test.txt community.cadence.com/.../BackstepTutorial.txtPythonGlyphPointwiseServer Connectionhttps://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66124/how-to-run-an-interactive-external-script-from-skillWed, 01 Jul 2026 11:57:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:39e0230a-7a09-4293-bbeb-27ff3690c0dcLoVyacheslavvVEMsHi, I need to launch an external script from SKILL. The script itself is not under my control - it may be a shell script, Python script, executable, or any other program. The important part is that the script may pause at arbitrary points and wait for user input from stdin. When this happens, I would like to prompt the user in Virtuoso (for example, using an AppForm), send the entered text back to the running process, and then continue its execution. I know about system() and ipcBeginProcess() , but I'm not sure whether SKILL supports this kind of interactive communication with a child process. Is there a supported way to: launch an external interactive process from SKILL; detect when it is waiting for input; send user input back to the process while it is running? Thanks in advance.Interactive ScriptSKILLhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66059/standardizing-design-settings-in-orcad-x-capture-cis/1408821Wed, 01 Jul 2026 11:09:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:04b2d93f-f017-4a0b-9550-d13f4894b6fbUlf KIt is the menu box itself I was referring to. When someone wants to place an arbitrary test and want to use eg. Courier, the text box in the add-text-canvas displays (Cadence) proportional text like tms roman, arial etc. This font cannot be changed. It is only possible to see the resulting alignment when having opted for courier only after the text has been placed in the schematic drawing. If the alignment (like having (white) spaces is wrong, the only way to correct it is to edit the text and in that edit box add or remove the (white) spaces.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66123/disable-cm-updates-or-audits-during-component-replace-through-tclWed, 01 Jul 2026 10:08:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a73d5503-cb9e-4206-a2b6-d50e3c3e2177PatEscherHello, we have written TCL code which programmatically replaces a component instance on the schematic with another one from the CIS library. For this we do a full replace, set all the properties and also consider any user properties and merge them. so a quite complex process, but everything is working fine. But we see some performance issues when doing this in OrCAD. Apparently OrCAD tries to update CM connectivity and XNets when we do this. we see in the status bar messages like "Pushing Connectivity changes in CM" , "ECSet Audit on Net Connectivity" Change, etc. is there any possibility to turn these updates off when we do the replace of the instance (it is not a single instance, but can be dozens or hundreds) and then later on turn it on again and do the 'full update' ? Can this be done through a tcl command, maybe like DboDesign_SetConnectivityUpdateTracking or maybe some Preference Settings? Thanks Patrickhttps://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66122/maegroupasparametricset-has-no-session-argumentWed, 01 Jul 2026 09:12:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0231d9be-20f1-4b27-a959-dd9b95b706a4SK202511261716I have a SKILL script running inside a form which at one point needs to create a parametric set for the Design Variables of a particular Test. I'm using maeGroupAsParametricSet for this, and it's worked well so far. Unfortunately I've just run into a problem: if I have multiple maestro windows open, maeGroupAsParametricSet starts to misbehave. Unlike other mae functions, it can't be provided a ?session argument. So if I run my form from the second maestro view that I've opened, it will fail to find the Test I specify, because it's looking for it in the first maestro view. I tested this with maeGetTestSession: if I don't provide the ?session argument, it returns nil, whereas if I do provide it, it runs successfully. This suggests to me that maeGroupAsParametricSet is looking in the first view by "default", and lacking a ?session argument it can't be told to look elsewhere. Am I misunderstanding something here, or is there a workaround for this? The warning message that appears after calling maeGroupAsParametricSet reads as follows: WARNING (ASSEMBLER-1602): Cannot find test in the setup database. The test name passed to this function does not exist in the setup database. Perhaps the name was misspelled or has not yet been created. The test needs to be created before calling this function. I'm on version IC23.1-64bmaestroVirtuosoSKILLhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66112/how-can-i-install-16-6-era-allegro-free-physical-viewer/1408820Wed, 01 Jul 2026 07:28:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9dee5b71-3205-41f7-abf8-240083afcf11CT202606302343community.cadence.com/.../db-doctor-23-1-download