https://community.cadence.com/cadence_technology_forums/Network with other Cadence users and Cadence technologists...en-USTelligent Community 12https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66054/python-version-of-cds_srr/1408613Tue, 09 Jun 2026 16:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6cc59cf7-2d7c-4c9a-87ad-4a385b3466cdAndrew BeckettThere is something called CDSPYTHONSRR which was introduced in IC23.1 ISR12 (it was available as a standalone kit on request before that) which allows you to read simulation results directly into Python. This doesn't cover everything that you can do with the ADE MATLAB interface (it's closer to the standalone Spectre toolbox for MATLAB), and there's no integration into ADE (so you can't have python expressions in the output). There's an enhancement CCR for that - 2052789 - with a few duplicates. If this is what you want, you should contact customer support (submit a case after logging in) and request a duplicate is filed on your behalf.https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66056/how-to-force-specify-which-variable-assembler-uses-as-x-axis-variable-for-plottingTue, 09 Jun 2026 15:38:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:918329a2-fe63-4c27-bb6d-6a2894f6bbd2AC202503109020Hello! I cannot figure out how to force/specify which variable Assembler uses as "x-axis variable" for plotting, when using corners for doing sweeps. I have prepared the following "toy example" that describes well the problem. I have a maestro view which a single test that does a single-point DC simulation of an NMOS, and calculates the gm from the opPoint results. The gate, drain and bulk voltages of the NMOS are defined by the variables VG, VD and VB, respectively. I also have 3 corners in my view: "CornerA__fixed_VD" = a "single-point" corner with an explicit value for the VD variable (<---this models a single-point corner used in my real-life application for some sort of calibration condition) "CornerB__sweep_VG" = a sweep of the variable vG (<--- this models an actual sweep of a parameter, as I would normally be interested in doing) "CornerC__sweep_VG_at_explicit_VB" = a sweep of the variable vG too, but this time also with an explicit value for variable VB. Here are 2 cases, with and without the problem: Case #1: If I run corners A and B together, and use the "Plot all" option from the results, Assembler uses "VG" as the independent variable for plotting, and I get a nice trace for the results of the sweep. Case #2: However, if I run corners A and C together, and plot as before, Assembler uses "VG" as the independent variable for plotting, and as a result I get a nonsensical plot with the results of the sweep scattered across several traces. So, how can I force Assembler to plot w.r.t. the "swept" variable "VG" in Case #2, just as it does for Case #1? Thanks, Adam. Note1: Please note this is a toy example: I know there are other ways to do sweeps, but the one I describe here is representative of the actual situation I encounter in my real scenario. Note2: I know about the "Swap Sweep Var" in VIVA, but unfortunately this doesn't solve my problem, as I would need to manually do this each time, which is not practical in my real scenario (Plotting Templates doesn't help either, they seem unable to work with traces created through the "Swap Sweep Var" method).https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/65949/productivity-toolbox-label-tune-does-not-support-truetype-fonts/1408611Tue, 09 Jun 2026 15:15:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b2c4ce67-d867-492a-8dfa-0c5f46f975fcJon LeeThe Label Tune issue has been fixed in (Version: June 01, 2026).https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66050/viva-trace-color-palette-rectangular-vs-smith-chart-plot/1408610Tue, 09 Jun 2026 14:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ee0a79b8-8ca0-42cb-8ddd-796552fdcb88TommasoFthanks, the envsetVal works great!https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66055/monte-carlo-simulations-with-a-multi-process-circuitTue, 09 Jun 2026 13:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:eb45b0d2-0775-4b23-8f50-200f12f16feaDarrell LWe are designing a module that will be made from two die bonded together to form a single device. Each die uses the same process, but come from different wafers. Some circuits will be split between the top and bottom die. I have used MTS options to cover corner cases between the two die, ie simulate the bottom circuits using an ss corner while the top circuit uses an ff corner. But I would like to simulate some circuits using Monte Carlo. It is not clear to me if the top die models and bottom die models will be treated independently, or if it will simulate both halves as if they are both on the same wafer. I want to see results where the process variation is completely independent between top and bottom, but the matching is still good between devices on the same half. Can you tell me how to get Monte Carlo results that show me results when the process varies independently for two sections of the circuit hierarchy, and mismatch occurs between devices on the same half? Thanks,VirtuosoMonte Carlo simulationMTShttps://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66054/python-version-of-cds_srrTue, 09 Jun 2026 12:34:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:eb69e434-f278-402e-9e38-0bd54e0fc847AC202503109020I like to use the cds_srr tool from matlab to process psf data from our simulations. Matlab requires an expensive license however and it is quite difficult to build easy-to-use command line tools for my users with it. Is there a python equivalent tool which does similar things?cds_srrpsfhttps://community.cadence.com/cadence_technology_forums/computational-fluid-dynamics/f/turbo/66045/analysis-of-flow-physic-within-tip-clearance-gap-of-an-unshrouded-high-pressure-turbine-blade/1408609Tue, 09 Jun 2026 11:44:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:25cc56ef-2467-4717-bc71-f5cdec7d9d21GauravWhen flow enters a tip gap with a sharp pressure-side corner, it undergoes a sharp contraction, resulting in a flow restriction known as a vena contracta. This phenomenon causes a separation bubble to form immediately after the corner. Whether the flow reattaches to the blade surface depends largely on the ratio of the blade tip thickness (t) to the gap height (h). There are two distinct scenarios based on this ratio: For thin blades, where the thickness is less than four times the gap height (t 4h), the physical surface area is sufficient for the flow to mix, recover, and reattach to the blade tip before exiting into the suction side. Specifically, given the blade's thickness being five times the gap height, reattachment of the flow is assured. In the context of unshrouded turbomachinery blades, the primary driving force behind leakage is the aerodynamic load on the blade, specifically the pressure difference between the high-pressure (pressure side) and low-pressure (suction side) surfaces. This pressure gradient effectively forces fluid through the clearance gap. The resulting over-tip leakage flow has two significant consequences: 1. Aerodynamic losses: These losses account for approximately one-third of the total losses in a turbine stage. Even a relatively small gap height, equivalent to just 1% of the total blade span, can result in a stage efficiency penalty of 1 to 3 percent or more. 2. Thermal losses: The high-velocity over-tip flow significantly enhances convective heat transfer coefficients, subjecting the blade tip region to extreme thermal loads.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/66037/how-do-we-map-special-symbols-like-power-and-ground-in-system-capture/1408608Tue, 09 Jun 2026 11:34:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:544e704d-60e8-4b68-9300-61bbb833238aWallEEIn Allegro System Capture, you can control most of the customizations through the CPM directives specified at the site/project level. If you need to configure the " Special Symbols " section to add/delete components like power symbols, flag bodies, and so on, the following steps should help: Navigate to your $CDS_SITE/cdssetup/projmgr/ and open the site.cpm file in a text editor. Note: If you do not have a site-level customization, you can do the changes at the project level by modifying the project CPM file. In the site.cpm file, locate the section START_CANVAS/END_CANVAS and add the following directive: POWER_SYMBOLS ' ! : : : ' Example: POWER_SYMBOLS '+1_5V!1.5V:standard:p1_5v:sym_1' Save the site.cpm file and launch Allegro System Capture. In the " Special Symbols " section, you should now see the configured power symbol.https://community.cadence.com/cadence_technology_forums/orcadx/f/orcad-x-presto-pcb/66032/connecting-mechanical-pins-to-a-ground-plane/1408607Tue, 09 Jun 2026 11:20:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:48aef126-d3e9-4928-ae03-f9cca57aadf2Ulf K"Been there". Advice: A l w a y s create connectors and other mechanical parts using "connectable"/passeive pins. Sometimes, connecting metal also acts as improving ESD protection. In regard to connectors, using "connectable pins" the layout designer then have a choise: Either connect them or, if it is desirable not to, simply add a "dangle" (x) = not connected. That will prevent a DRC error. IMHO, the only time a mechanical (ie: solderless pad (hole)) should be added is when creating a part that has guide holes without copper. And that is done in the layout editor. Just make sure that a suitable copper keep-out area around these holes are added. Crating schematic symbols with multiple pins of same net such as a thru-hole or end launcher SMA connector with 4 ground pins can be accomplished so that only one ground pin is visible is using the "pack short" property, but sometimes this rises quesrtion during auditing. I usually takes the easy way out and simply adds the four gnd pins apart from the center (RF) pin.https://community.cadence.com/cadence_technology_forums/orcadx/f/orcad-x-presto-pcb/66032/connecting-mechanical-pins-to-a-ground-plane/1408606Tue, 09 Jun 2026 10:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1fa2bcd5-bfcc-4ade-a4cd-3a9e10bc26dfJeetAre you connect Mechanical pins present in a component in schematic to SMA connector pins also or ground plane ? Which version of the tool you are using ?https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66050/viva-trace-color-palette-rectangular-vs-smith-chart-plot/1408605Tue, 09 Jun 2026 09:54:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d4734a38-dfb4-4463-83c9-384d984afaacAndrew BeckettHi Tommaso, It seems that red and green are omitted by default from the default color bank for Smith Charts (probably because of the traditional use of these colours on Smith Charts for the axes). You can however override the default color bank as follows: envSetVal("viva.graph" "colorBank" 'string "red, yellow, lightgreen, cyan, blue, magenta, green, pink") that's just an example - in which case the color banks become unified between the charts. I think the colors would then be aligned (you could also use Window->Assistants->Customise Trace Groups to set the colors across the windows based on some criteria if you want to alter it). What I'm not sure about is the default (the default color bank is "default", rather than a list of colors). You might want to contact customer support - there is an existing Cadence Change Request (CCR) #2832817 on this. Nothing being done at the moment - the colorBank env var is the workaround. Andrewhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66051/how-to-successfully-place-a-custom-titleblock-in-the-tcl-instructions-for-creating-an-opj/1408603Tue, 09 Jun 2026 08:32:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6b6af561-29f0-4170-987f-1b94d8eb6e80TechnoBobbyHi FK202606088435 , Could you please confirm how you are trying to share the TCL, are you attempting to upload the *.tcl file directly to the forum, or are you trying to copy‑paste the commands into the reply thread? you can try pasting the script in smaller parts or share only the relevant portion causing the issue.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/62930/how-to-get-a-report-showing-padstack-and-shapes-used-in-it-library-path/1408602Tue, 09 Jun 2026 08:15:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0a389b64-8449-41c5-9feb-4cb5f073bacasteveSorry but I'm unaware of the skill required for the module report. Hopefully someone else may be able to modify the orignal skill that is included in this post earlier to give you what you need,https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66048/add-layers-menu-is-grayed-out-in-cross-section/1408601Tue, 09 Jun 2026 08:08:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e2caff01-d2c1-4edf-9add-1ae44167278esteveLook at the Lock tab in the cross section GUI (at the bottom) and uncheck the Add Layers box.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66051/how-to-successfully-place-a-custom-titleblock-in-the-tcl-instructions-for-creating-an-opj/1408600Tue, 09 Jun 2026 07:44:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f554c6ee-86eb-48a5-85d9-e87052c63535FK202606088435Hi TechnoBobby, I've tried several times, but I still can't paste my TCL command here. I also can't share it with you via Google Drive sharing link. Is there any other way to share my TCL command? Thank you for your assistance in replying.https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66053/guidance-on-reducing-rlck-extraction-size-for-pdn-inductance-analysis-quantus-pvsTue, 09 Jun 2026 07:31:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9435da8f-d304-441d-95bb-f507e485f333baltaciHello, I am using IC 23.1-64b.43. My goal is to estimate the series resistance (R) and series inductance (L), including mutual inductance , between the supply (VDD) and ground (VSS) pads and a digital core in a power integrity analysis of a digital circuit. I am primarily interested in the PDN impedance behavior between VDD and VSS . To reduce parasitic extraction complexity and the size of the extracted view, I simplify the design by keeping only the top-level metal power distribution network (VDD and VSS) between the pads and on top of the digital block . I remove active devices and the digital core, since the internal core behavior (including decoupling capacitance) is already known and modeled separately. I am currently using the PVS Quantus RLCK extraction flow . However, the resulting extracted netlist becomes very large (~2.5 GB), mainly due to inductive segmentation and dense mutual coupling terms. As a result, Spectre AC simulation fails due to swap/memory exhaustion. Could you please advise: Is there a way to reduce the size of the extracted RLCK netlist in Quantus PVS, by reducing the number of lumped elements generated during parasitic extraction (e.g., inductive segmentation and mutual coupling complexity), while still preserving sufficient accuracy for PDN AC behavior between VDD and VSS? In other words, is there a supported method to obtain a more compact or reduced-order lumped representation of the inductive network in order to reduce simulation memory requirements and prevent swap/memory exhaustion during Spectre analysis? Outside of the standard Quantus PVS RLCK flow, is there an alternative Cadence-recommended approach or tool to achieve this objective more efficiently? My main goal is to obtain the AC impedance behavior of the PDN (VDD/VSS) from pads to the digital core, effectively capturing series resistance and inductance (including mutual coupling), but in a more computationally efficient or reduced-order form suitable for simulation. Thank you.Power IntegrityInductance ExtractionQuantushttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66051/how-to-successfully-place-a-custom-titleblock-in-the-tcl-instructions-for-creating-an-opj/1408594Tue, 09 Jun 2026 06:45:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a71b9821-fecd-4125-a075-b52f211c6902TechnoBobbyHi FK202606088435 , Since the same TCL commands works in a manually created DSN, the issue is likely related to when and where the title block is being applied in the script. Could you confirm whether your script places the title block after the DSN is fully open and the page is created and set as active? Sharing your TCL snippet will help narrow this down. For further details, you can refer to below article on ASK portal: Article (20498203) Title: How to place custom title blocks based on page sizes in OrCAD X Capture URL: support.cadence.com/.../ArticleAttachmentPortalhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/51640/generate-orcad-netlist-with-orwirelist-dll-using-tcl-script/1408593Tue, 09 Jun 2026 06:34:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:bb46dd72-dc61-48a9-9be7-4f343d479005TechnoBobbyHi CA20240926987 , If you're looking to export similar format data using TCL script, you can try below code. Hope this helps! proc pinConnectivityReport {} { if {[file exists "pinConnectivity.txt"] == 1} { file delete "pinConnectivity.txt" } set lPathCS [DboTclHelper_sMakeCString] [GetActivePMDesign] GetName $lPathCS set lPath [file dirname [DboTclHelper_sGetConstCharPtr $lPathCS]] set lSession $::DboSession_s_pDboSession DboSession -this $lSession set lNullObj NULL set lStatus [DboState] set lDesign [$lSession GetActiveDesign] if {$lDesign == $lNullObj} { puts "ERROR: No active design." return } set lSchi_Name [DboTclHelper_sMakeCString] set lPinNameCS [DboTclHelper_sMakeCString] set lPinNumberCS [DboTclHelper_sMakeCString] set lNetNameCS [DboTclHelper_sMakeCString] set lRefdesNameCS [DboTclHelper_sMakeCString] set lReport [open "pinConnectivity.txt" a+] if {$lDesign != $lNullObj} { set lSchematicIter [$lDesign NewViewsIter $lStatus $::IterDefs_SCHEMATICS] #get the first schematic view set lView [$lSchematicIter NextView $lStatus] set lPage_Name [DboTclHelper_sMakeCString] while { $lView != $lNullObj} { #dynamic cast from DboView to DboSchematic set lSchematic [DboViewToDboSchematic $lView] $lSchematic GetName $lSchi_Name set lPagesIter [$lSchematic NewPagesIter $lStatus] #get the first page set lPage [$lPagesIter NextPage $lStatus] # puts [DboTclHelper_sGetConstCharPtr $lSchi_Name] while {$lPage!=$lNullObj} { #placeholder: do your processing on $lPage $lPage GetName $lPage_Name # puts [DboTclHelper_sGetConstCharPtr $lPage_Name] set lPageName [DboTclHelper_sGetConstCharPtr $lPage_Name] set lPartInstIter [$lPage NewPartInstsIter $lStatus] set lInst [$lPartInstIter NextPartInst $lStatus] while {$lInst != $lNullObj} { puts $lReport "++++++++++===========+++++++++++++" $lInst GetReferenceDesignator $lRefdesNameCS set lRefdes [DboTclHelper_sGetConstCharPtr $lRefdesNameCS] set lPinIter [$lInst NewPinsIter $lStatus] set lPin [$lPinIter NextPin $lStatus] while {$lPin !=$lNullObj } { # puts $lPin $lPin GetPinName $lPinNameCS set lPinName [DboTclHelper_sGetConstCharPtr $lPinNameCS] # puts "$lPinName pinName" $lPin GetPinNumber $lPinNumberCS set lPinNumber [DboTclHelper_sGetConstCharPtr $lPinNumberCS] # puts "$lPinNumber pinNumber" set lWire [$lPin GetNet $lStatus] # puts $lWire if {$lWire != $lNullObj} { $lWire GetNetName $lNetNameCS set lNetName [DboTclHelper_sGetConstCharPtr $lNetNameCS] # puts "$lRefdes.$lPinNumber.$lNetName.$lPageName" puts $lReport "$lRefdes.$lPinNumber.$lPinName.$lNetName.$lPageName" # puts [DboTclHelper_sGetConstCharPtr $lNetNameCS] } #get the next pin of the part set lPin [$lPinIter NextPin $lStatus] } delete_DboPartInstPinsIter $lPinIter puts $lReport "++++++++++===========+++++++++++++" set lInst [$lPartInstIter NextPartInst $lStatus] } delete_DboPagePartInstsIter $lPartInstIter #get the next page set lPage [$lPagesIter NextPage $lStatus] } #get the next schematic view delete_DboSchematicPagesIter $lPagesIter set lView [$lSchematicIter NextView $lStatus] } delete_DboLibViewsIter $lSchematicIter } close $lReport exec {*}[auto_execok start] "" "$lPath\\pinConnectivity.txt" } pinConnectivityReporthttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/66019/customized-gui-to-control-artwork-film/1408592Tue, 09 Jun 2026 06:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:659c2dff-333e-48ef-b126-10b0ac18fbdaMZ20250602835Dear techiecs, glad to give a update: I created the skill with your help( axlFilmCreate ) and it works as i expect. Many thanks again for your help and support. Many thanks again and best Regards Moyanhttps://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66052/parameterization-of-hidden-parametersTue, 09 Jun 2026 06:08:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:5e01a4f3-ecd0-4558-8210-b193de82ebbcJT202409108313Is there a way to add to Assembler's parameter list those device parameters that may be hidden (AKA Display Condition is not blank/t)? Constraint is that the Display Condition cannot be edited but the condition can be triggered once the device is used in a circuit. I can trigger it to show, add it to parameter list, then trigger it to hide again and I think that would pose no problem when I sweep it. However, that would be much of a hassle if I will do it for all instances of the device on different subblocks. Is there a way to make it faster?