Sigrity - Recent Threads

Why Cphy compliance demo simu IL result not pass? only 400mil length

JB202607048610 — Sun, 05 Jul 2026 05:05:11 GMT

Got Questions on Sigrity? Let’s Answer Them—LIVE on Wednesday, June 24th

Renu Vibha — Thu, 18 Jun 2026 13:23:47 GMT

Curious about the latest features? Facing real-world design challenges you’d like to crack faster?

This is a much awaited interactive live session with Cadence experts to get the answers you need—right when you need them.

Join us here on June 24, 2026 at 7:30 – 8:30 PM IST

Topics

PCB & IC Package S-Parameter Model Extraction
PDN Voltage Drop Analysis
High-Speed Design Simulation

This is your opportunity to:

Ask live questions
Learn from real use cases
Exchange insights with peers

Bring your challenges. Share your perspective. Be part of the conversation.

Sigrity: 'Getting Started' to 'Sign Off'

Sumith — Thu, 18 Jun 2026 06:17:27 GMT

As a new Sigrity user, what was the first setup, modeling decision, or workflow change that helped you move from ‘getting started’ to getting meaningful SI/PI results—and what do you wish you had known on day one?

PowerDC Queries

cistheta07 — Tue, 26 May 2026 07:46:03 GMT

Hi everyone,

I’m currently working on IR drop analysis using Cadence Sigrity PowerDC and exploring some of its advanced setup options. As I go through the workflow, I have a few questions related to material definition and thermal analysis.
How can I define a custom material file?
Does PowerDC support IR drop simulation across different temperature points?
What engine is used for thermal analysis in PowerDC?
Can we model active components and include the same in IR drop simulation?

Any guidance or insights would be greatly appreciated.

Sigrity - Tip of the week: How to use multiple IBIS models for LPDDR5X controller (DQ + WCK)

ALLpdf — Fri, 22 May 2026 03:52:53 GMT

Parallel Bus Analysis (PBA) and Topology Workbench allow only one controller block, which can load only one IBIS file at a time.

The simplest approach is to open both IBIS files in a text editor, copy the WCK model block from its IBIS file into the controller’s IBIS file, and then assign the WCK pins to this imported model.

The workaround is to merge both IBIS models into one combined IBIS file. This allows SystemSI/TopXp to read both DQ and WCK models from a single IBIS file while mapping each model to its corresponding pins. Thus, this approach merges the content of both files while keeping them logically separate under different [Model] names.

You can use the following template format:

-----------------------------------------------------------

[IBIS Ver] 5.0
[Comment] Combined IBIS for DQ + WCK

[Component] DDR_Controller
  [Pin]
  1   DQ0     DQ_Model
  2   DQ1     DQ_Model
  3   WCK0    WCK_Model
  ...
[End Component]

[Model] DQ_Model
  ... (contents from the first IBIS file)

[Model] WCK_Model
  ... (contents from the second IBIS file)

--------------------------------------------------------------------

Steps:

Open the DQ IBIS file in a text editor.
Copy the entire WCK model block from the second IBIS file.
Paste it below the DQ model block.
Add a single combined [Component] section with all the pins assigned correctly.
Ensure the following:
- Only one [IBIS Ver] line exists.
- Only one [Component] block exists.
- Each pin references the intended model name.

Once merged, the combined IBIS file can be assigned to the controller block without tool limitations.

PowerDC asi_spd.dll

AC202503029240 — Tue, 28 Apr 2026 18:22:27 GMT

Hi

while loading layout file in PowerDC I'm getting below error

Error: Failed to load asi_spd.dll, check the program directory to find asi_spd.dll

even though the bin folder contains asi_spd.dll

kindly helpt to resolve

thanks in advance

Regards,
Anthony

POWERDC

JL202509104850 — Tue, 21 Apr 2026 06:27:24 GMT

1. Why is the input side copper no show the Delta W data.

Power SI - Query on Retrieving Connected Objects from a Net in PowerSI 2021.1 Using TCL

ABIKRISHNA — Mon, 05 Jan 2026 07:11:48 GMT

Hello Team,

I am currently working on automating a task in PowerSI 2021.1 using a TCL script. I would like to retrieve all objects connected to a given net or any other objects, similar to how we use axlDBGetConnect in Allegro.

Specifically, when I provide a net name, I want the script to return all connected elements such as:

Vias
Components / pins
Traces / clines / shapes

In Allegro, axlDBGetConnect allows us to easily find all elements connected to a given DBID. I am looking for an equivalent or recommended approach in Sigrity PowerSI TCL to obtain this connectivity information.

Could you please let me know:

If there is a direct TCL API or command in PowerSI to query all objects connected to a net
Or, if not, what is the recommended workflow to extract this connectivity data programmatically

downloadind sigrity by university program

YV202508175258 — Sun, 28 Dec 2025 12:25:07 GMT

Hello ,after I sent a request so sigrity I got the following E-mail.

I got to the shopt web page but i dont see the sigrity powerSi link to download.

Is there a direct link I could use?

Thanks.

Thank you for your recent inquiry.

Students and professors have access to academic trials for CFD Simulation, Allegro PCB Design, Microwave Office, OrCAD X Multiphysics Analysis (Clarity, Celsius, Sigrity) available OnCloud through the Cadence University Program. You will need to use your university email address to get the free academic version. Other technologies are not offered at this time.

Go the Cadence University Program page

Select a product and click on ‘Free Access’
Click on ‘Join or log in’ to start today
Login if you already have a Cadence account
If not Click on ‘Create an Academic Account’

Set up OptimizePI

KN202502107649 — Mon, 08 Dec 2025 10:29:29 GMT

Hi everyone,

I’m running a PDN simulation for the VDD rail on my board and I’m not sure how to set up the VRM model and the impedance observation in OptimizePI.

On my board the VDD rail is split into two net names:

VDD_MB: this comes from a connector and gets power from another power board.
After the connector the power goes through resistor R10.
VDD: this is the net after R10 and it powers the load IC (U1).

So the topology is:
external VRM → connector → net VDD_MB → R10 → net VDD → U1.

My questions:

For this topology, should I assign the VRM model to VDD_MB or to VDD in OptimizePI?
For impedance observations, is it enough to create one observation at U1_VDD_GND, or should I also create an observation at the connector/net VDD_MB?

Any suggestions or example setups would be greatly appreciated.

Thank you very much,
Kaydee

How to get the via backdrill layers through TCL script.

ABIKRISHNA — Wed, 19 Nov 2025 06:21:06 GMT

Hello Team,

I am currently working on automating a task in PowerSI 2021.1 using a TCL script. My goal is to remove the backdrill from vias based on a given net name. We are able to retrieve the vias associated with the net, but we are unable to get the details of each via connecting layers using script.

Could you please advise on how to identify the backdrill start and end layers of via through TCL.

Cadence Connect Ahmedabad, India | Join us in Ahmedabad for an exclusive seminar on System-Level Design and Analysis on November 27, 2025

Renu Vibha — Mon, 17 Nov 2025 06:48:25 GMT

Join us in Ahmedabad for an exclusive seminar on System-Level Design and Analysis!

As design complexity grows, engineers face increasing pressure to deliver faster, more accurate results.

This session brings together industry experts to showcase how AI-driven automation, intelligent methodologies, and advanced multiphysics analysis are transforming PCB design and verification.

Why Attend?
Discover smarter ways to manage design complexity
Learn how data-driven automation accelerates productivity
Gain insights into optimizing electrical, thermal, and EM performance

Ahmedabad | November 27, 2025
Register now: https://events.cadence.com/CadenceCONNECT_PCB_Ahmedabad?utm_source=SM&utm_medium=SM&utm_cam…

How to assign a group of BGA pin in OptimizePI

HASAN2024 — Thu, 13 Nov 2025 14:16:25 GMT

Hi there,

I got stuck, with a simulation in OptimisePI,

My board is bit different; it has 4000 BGA pins in bottom and over 500 decaps.

Now , let me give you some examples then it will be easy for you to understand what I want to do.

Power Integrity analysis

Impedance checking

IC Device Power Pin Inductance Analysis

Setup

Frequency 1MHz (default)

VRM not defined

All VDDC caps are shorted

Need to simulate :

BGA pin inductance( Inductance observed at VDDC BGA pins ,BGA pins are defined as IC device.

Let me know how I can make net for this type of BGA pin row,

https://drive.google.com/file/d/1PtezuAY4AOoQTkx9QOZCZwMRaqkof9gE/view?usp=drive_link

BGA pin inductance a polygon is placed over the BGA row and the capacitor package keep-out/ mask is present there.

And most importantly, I don’t know how the engineer has ordered the BGA row with caps, he mentioned in his simulation result like, Row AG-BG/ Row BJ-CJ/ Row CL-DJ, where the caps are considering vertical and horizontally placed in layout. Any axis rotation?

Cadence Connect Hyderabad, India - Register for Futuristic Design Authoring for Integrated Signal, Power, and Thermal Design Session on Nov 25

Renu Vibha — Tue, 11 Nov 2025 10:08:37 GMT

Join us in Hyderabad for an exclusive seminar that dives into the evolving challenges of system-level design and analysis. As design complexity grows, engineers are under pressure to deliver faster, more accurate results without compromising innovation.
This session brings together domain experts to showcase how intelligent design methodologies, AI-driven automation, and advanced multiphysics system analysis are reshaping the way teams approach schematic capture, layout, signal, power, thermal integrity, and electromagnetic simulations.

Why Attend?

Discover smarter ways to manage front-end design complexity and accelerate design intent capture
Learn how data-driven automation is transforming layout productivity and verification cycles
Explore new approaches to signal and power integrity analysis for faster convergence and higher accuracy
Gain practical insights into optimizing design performance across electrical, thermal, and EM domains

Whether you're building next-gen systems or streamlining design cycles, this seminar will equip you with actionable strategies to stay ahead.

Event Details
Date: November 25, 2025
Time: 9:30am – 4:30pm IST
Location: Novotel Hyderabad Convention Centre (HICC), HITEC City, Hyderabad

Sigrity Aurora Create Pin Pairs Greyed out

Don2009 — Mon, 10 Nov 2025 10:49:37 GMT

Hi Everyone,

I am in the middle of learning Sigrity Aurora through an online course and have come across a problem which has brought me to a halt. I am trying to add constraints to an ECSET but it is greyed out.

I am clicking setup>constraints>electrical, right clicking on the net and select Explore Topology which then opens the topology explorer, select the ECSet tab, click Set Topology Constraints, click the green + symbol beside Impedance and when the Create Pin Pair - Impedance window opens it's greyed out.

Any ideas or help on what is causing this and more importantly how to get this sorted is much appreciated.

Thanks everyone!

Issue with Impedance/Reflection Analysis in Sigrity Aurora 23.1

AT202510166839 — Tue, 21 Oct 2025 03:51:25 GMT

Hello Cadence Community,

I am using Sigrity Aurora 23.1 and while performing reflection and impedance analysis, the error log initially showed:

The database version of the design file is not compatible with the Sigrity release version that is currently installed. Refer to the Compatibility Matrix section of the Installation Guide for information on the compatible Sigrity release version.

To resolve this, I installed Hotfix 2, which is compatible with Sigrity Aurora 23.1 and PCB Editor 23.1 base version.

My board design was originally done in Allegro 17.2, so I:

Saved the board in PCB Editor 23.1,
Then opened it in Sigrity Aurora 23.1.

After installing Hotfix 2, while simulating the analysis, the database compatibility issue was resolved, but a new problem arose:

invalid command name "sigrity::selectnet"

The net selection workflow seems to be working as expected, but this message still appears in the log and may be affecting the analysis.

Could someone guide me on:

How to handle this sigrity::selectnet issue in HF2, & complete the simulation.

Any suggestions or workarounds would be highly appreciated.

Thank you!

Anusree T V

Project Engineer

Centre for Development of Advanced Computing

Ciarity PCB Extraction Suite issue 2024

jasonman — Mon, 08 Sep 2025 03:02:43 GMT

Hi Cadence,

i'm Jason

I want to try use "Ciarity PCB Extraction Suite issue 2024" extracted PKG

but always show error

below to

1. E1699 Load w3d mesh data error

2. Internal error 58807 no intersection found between curves

i dont know any idea how to kill it

could you have any suggestion

B.R

Thanks

Jason

Output File Paths

LL202408212637 — Fri, 18 Jul 2025 22:39:06 GMT

When I run a powersi simulation, all the files get dumped in my current working directory where I execute the batch mode commands to run powersi. Is there a way to change the way powersi dumps the files so that I can store the log files in a specific folder, the spd files in a specific folder, etc? I am using a python script to import an options file but I'm not sure if the file paths within the file manager section of the xml are compatible with relative paths, they are only using absolute paths.

Executing python commands through terminal

LL202408212637 — Thu, 10 Jul 2025 17:57:19 GMT

I've been able to execute tcl scripts through the terminal by running & "C:/path/sigrity2024.1" -tcl "tclscript.tcl". I was wondering if there is an equivalent for running a python script as I see that python support is being added and all the equivalent tcl commands can be converted to its python equivalent?

Different Results with same layout

PM202507106649 — Thu, 10 Jul 2025 13:08:37 GMT

Hi Everyone,

I was doing a PDN analysis for a VDD power net, since the layout file was really heavy i split it into 4 number of layouts since there were 4 VDD nets going to 4 different DUT's. When i simulated the layout with all the 4 VDD in one layout file with the decoupling capacitors ESL at 0.2 nH i got the impedance around 20mOhm, now with the same layout when i split it into 4 individual layout one for each VDD and the same decoupling cap with same ESL the result is 23mOhm. I do not understand why this difference occurs between simulating the entire layout and the manually cut individual layout ?

If someone could please explaint why this is the case would be really helpful for me to understand for the next time.

Thank you

PDN Impedance Simulation

HirosakiOnda — Tue, 10 Jun 2025 08:33:36 GMT

Hi everyone,

I have a trouble with my PCB high-speed designs.

I have 2 designs called Design A and Design B with details information for my POWER like that:

Design A have 20 VCC De-CAPs with total capacitance value is 178.6uF

Design B have 33 VCC De-CAPs with total capacitance value is 430.4uF

In theory, the impedance in Design B is better than (Lower Impedance) the impedance in Design A

In fact, when I run PI simulation about the PDN imdedance for this POWER. I see that the impedance at AC range ( > 2MHz) is OK but the DC range ( 0 to 2MHz) is NOT OK.

The DC range, the impedance in Design B is higher than the impedance in Design A. It's NOT good! I expected the opposite. I expect these 2 DC results to be at least equal about the Impedance.

Can anyone explain this simulation result to me?

Thank you!

Electrostatic Discharge (ESD) Analysis using SpeedEM: Ensuring Electronic System Reliability

SimTech — Fri, 23 May 2025 13:05:48 GMT

Electrostatic Discharge (ESD) is a common cause of hardware failures in electronic systems. As devices become increasingly complex, the need to address ESD issues at the system level has grown. In this post, we will explore the importance of system-level ESD simulations and how SpeedEM can be used to perform ESD analysis on package designs.

The Need for System-Level ESD Simulations:

Traditionally, ESD protection has been focused on the IC level, with protection diodes and other means used to prevent damage from ESD events during manufacturing and handling. However, as devices become more complex and interconnected, system-level ESD protection mechanisms are needed to handle ESD events in fully operational systems.

IEC-61000-4-2 Standard:

The IEC-61000-4-2 standard defines four levels of ESD protection using two different discharge mechanisms: contact discharge and air discharge. The standard provides a physical test setup and defines a typical discharge event current waveform. This waveform is characterized by a peak current and specific current values at 30ns and 60ns.

The following image shows the physical test setup defined by the standard:

A typical discharge event produces the following current waveform. In the following image, the peak current is given above, while the current at 30ns and 60ns are also given by the standard:

SpeedEM ESD Analysis:

SpeedEM can be used to perform ESD analysis on package designs. The following steps are involved:

Providing the default ESD gun model circuit: This involves injecting the ESD current into the package design using a default ESD gun model circuit that follows the IEC-61000-4-2 standard.
Specifying the necessary steps to observe the ESD phenomenon: This involves setting up the simulation to observe the ESD phenomenon on a package design.

Analyzing the ESD waveform: This involves analyzing the ESD waveform to determine the necessary steps to set up ESD protections.

Benefits of SpeedEM ESD Analysis:

Using SpeedEM for ESD analysis provides several benefits, including:

Early detection of ESD issues: Performing ESD analysis early in the design cycle can help identify potential ESD issues before hardware becomes available.
Optimization of ESD protections: SpeedEM can be used to optimize ESD protections and ensure that the design meets the required standards.
Reduced design cycles: By performing ESD analysis virtually, design cycles can be reduced, and the need for physical prototypes can be minimized.

To explore ESD Analysis using SpeedEM, refer to

Electro Static Discharge (ESD) Analysis for Packages with Sigrity SpeedEM

Electrostatic Discharge (ESD) is a significant threat to electronic systems, and system-level ESD simulations are necessary to ensure that designs can withstand ESD events. SpeedEM can be used to perform ESD analysis on package designs, providing early detection of ESD issues, optimization of ESD protections, and reduced design cycles.

Do you have any experience with ESD analysis using SpeedEM? Share your thoughts and experiences in the comments below!

Team SimTech

Cadence Design Systems

Extracting RLC parasitics for Packages at Layout Level

SimTech — Fri, 25 Apr 2025 12:05:10 GMT

The latest release of the Allegro X APD in Cadence IC Packaging 24.1 features a new XtractIM workflow, designed to simplify the process of extracting RLC parasitics in a package design.

The XtractIM workflow is part of the Aurora workflows for In-Design Analysis (IDA) and is designed for high-speed analysis and checking within the Sigrity Aurora environment.

The other Aurora Workflows to name few are

Design Setup Workflow: Prepares the design environment for analysis.
Impedance Workflow: Automates design tasks and analysis related to impedance.
Coupling Workflow: Focuses on analyzing coupling effects between signals.
Crosstalk Workflow: Identifies and mitigates crosstalk issues in designs.
Reflection Workflow: Used to identify and fix reflection issues on signals.
Return Path Workflow: Analyzes return paths for signal integrity.
IR Drop Workflow: Assesses voltage drop across power distribution networks.
Power Inductance Workflow: Evaluates inductance effects on power delivery.
Interconnect Model Extraction Workflow: Extracts models for interconnects to improve simulation accuracy.

This intuitive flow enables package layout designers to efficiently extract critical data, including per-pin resistance and inductance of power/ground nets and net length, DC resistance, inductance, capacitance, and delay of each signal/power net.

Here is a sample result table for a power net:

One of the key advantages of the XtractIM workflow is its ease of use. The step-by-step process guides users through the analysis, ensuring that all necessary steps are completed before proceeding to the next stage. This streamlined approach not only saves time but also reduces the risk of human error, resulting in more accurate and reliable results.

The XtractIM workflow also offers a high degree of flexibility, allowing users to extract a model from either a full package or selected nets of a package. This feature enables designers to focus on specific areas of interest, fine-tuning their analysis to meet the demands of their design.

Furthermore, the XtractIM workflow integrates seamlessly with the APD canvas, enabling users to select nets directly or via the (X)Net Selection window. This makes it easier to identify and analyze the performance of individual nets, facilitating a more detailed understanding of the package's behavior.

Diff Pairs selected in canvas or in (X)Net selection:

In addition, the XtractIM workflow can be accelerated using distributed computing, allowing designers to take advantage of high-performance computing resources to speed up the analysis process. This capability is particularly valuable when dealing with complex designs, where simulation times can be significant.

The analysis results are presented in a clear and concise manner, with options to view XtractIM tables and visions. The Simulation Table window provides a comprehensive overview of the simulation data, while the vision overlay feature enables designers to visualize the results directly on the APD canvas. This visualization capability is invaluable in identifying potential issues and optimizing the package design.

In conclusion, the XtractIM workflow in the APD is a powerful tool that streamlines the package analysis process, enabling designers to extract critical data quickly and accurately. Its ease of use, flexibility, and high-performance capabilities make it an indispensable asset for package layout designers seeking to optimize their designs and deliver high-quality results.

Mitigate Signal Reflection Issues in High-Speed Designs

JavierAlvarado — Wed, 23 Apr 2025 16:32:24 GMT

High-speed designs are prone to problems like reflection and ringing, which can be detrimental to signal integrity. To avoid these issues, it's crucial to simulate and analyze your designs proactively.

Simplify Signal Reflection Analysis with Integrated Workflows

Our intuitive analysis workflows allow you to simulate, analyze, and resolve signal reflection problems directly on your canvas. Simply select the nets of interest and initiate the analysis.

Easily Identify and Fix Signal Reflection Issues

In this example, we're analyzing a DDR data net. The signals are color-coded to indicate the level of reflection, and you can view detailed information in a table. The red-coded DQ net shows a negative ring back margin, indicating excessive ringing due to impedance mismatch caused by a split plane.

Design Tip: Optimize Your Design

To fix this issue, move the reference plane to minimize impedance mismatch and re-run the analysis.

The Reflection Table provides a comprehensive view of voltage and timing measurements, including ring back margin, propagation delay, and more.

Common Causes of Signal Reflection

Impedance mismatches, return path gaps, and signal discontinuities can all contribute to signal reflection. With our integrated analysis, you can quickly identify and fix these issues.

Get Started with Reflection Analysis

Click this Ask Portal link to get a material reference about how to run Reflection Analysis in Sigrity Aurora Workflow.

Best regards,

Javier Alvarado

EDA Evolution: How Python Automation is Redefining the Sigrity User Experience

ShivaShankarM — Sun, 23 Mar 2025 03:43:09 GMT

In the world of electronic design automation (EDA), Sigrity tools such as PowerSI, PowerDC, and Clarity 3D solver are industry-standard solutions for power integrity, signal integrity, and 3D electromagnetic analysis. However, manual operation of these tools sometimes can be time-consuming and prone to errors. This is where Python automation comes in – a game-changer for Sigrity users. You can explore how Python can be used to automate Sigrity tools, increasing productivity and reducing manual labor.

Why Python?

Python is a popular, versatile, and easy-to-learn programming language that has become a de facto standard in the EDA industry. Its simplicity, and extensive libraries make it an ideal choice for automating Sigrity tools. With Python, you can create scripts that interact with Sigrity tools, automate tasks, and even integrate with other tools and workflows.

Python’s flexibility and rich ecosystem makes it a valuable API for engineers working in Signal Integrity (SI) and Power Integrity (PI) domains, thus enabling them to streamline design workflows, analyze complex data sets, and optimize designs for improved performance and reliability.

Cadence Sigrity support both Python and Tcl to automate your tasks. Python is an object-oriented programming language that offers the following advantages over Tcl:

Ease of use: Python syntax is simpler and more consistent than Tcl.
Extensive libraries: Wide range of libraries are available for use in Python, as required.
Portability: Python programs can be run across platforms without modifying the program code.
Readability: Python code is easy to understand and, therefore, easy to maintain and debug.
Speed: Python is much faster than Tcl when running typical codes.

Python automation can significantly improve your productivity when working with Sigrity tools like PowerSI, PowerDC, and Clarity 3D Solver. By automating tasks such as simulation creation, execution, and result processing, you can focus on higher-level tasks and reduce manual labor. You can get started with Python automation for Sigrity tools and take your productivity to the next level.

Sample Python script:

In Sigrity, users can automate tasks using Python scripts by either browsing and selecting the script file and clicking ‘Play Python’ icon from menu, (or) by copying and pasting the script’s content directly into the Python Command window and then clicking the ‘Run’ button.

(or)

Click here for more details on how to automate sigrity tools using Python in an easy and efficient manner.

Share your thoughts on the following statement:

“Python automation has the potential to transform the way I work with Sigrity tools. I'm excited to explore its possibilities and improve my productivity.”

Team SimTech

Cadence Design Systems