Sigrity - Recent Threads

What has been your most challenging Signal Integrity issue in a recent design, and which Sigrity features or workflows proved most valuable in diagnosing and solving it?

Sumith — Thu, 10 Sep 2026 07:18:11 GMT

How to include exact 0 Hz (DC) point in PowerSI to avoid low-frequency extrapolation?

cistheta07 — Thu, 10 Sep 2026 06:42:54 GMT

Hi Experts,

I am currently working on a high-speed PCB design that requires both Power Integrity (PI) impedance profiling and time-domain transient SPICE simulations. My analysis needs to cover the entire frequency range-from static DC up to several gigahertz.

When I run standard AC S-parameter extractions in Hybrid Solvers, the solver extrapolates data at low frequencies (below 100 kHz down to 0 Hz). As a result, the low-frequency plane resistance ( $R_dc$ ) isn't accurate, which distorts low-frequency die-bump impedance ( $Z_die)$ plots and results in miscalculated bulk decoupling capacitor requirements.

Additionally, if I run transient circuit simulations using these extrapolated models, my SPICE solver often experiences convergence issues due to non-physical DC offsets.

How can I configure PowerSI to include an exact 0 Hz static DC point in my S-parameter extractions so I don't rely on mathematical extrapolation?

Thankyou in advance.

Automated Layout Validation During PCB/Package Translation in Sigrity & Clarity

cistheta07 — Mon, 17 Aug 2026 06:45:48 GMT

Hello Experts,

Is there a way to perform layout integrity checks during PCB or IC Package translation into the Sigrity/Clarity environment?

Specifically, can the tool automatically detect issues such as floating nodes, short circuits, and open circuits during translation, and provide warnings or mark the error locations? Additionally, is there a TCL command available to enable this validation in workflows?

Thank you.

Why does the PowerDC report show negative current through component pins or vias?

ALLpdf — Thu, 13 Aug 2026 03:21:23 GMT

When the current is negative, it means that the current is flowing from sink to VRM. A possible reason could be that there are two voltage sources connected to the component directly or through some other component, and the higher voltage source is forcing current to the lower voltage source though the component. As a result, the current through the component is negative and the higher voltage is changing the lower voltage.

Consider the following result from a VRM at 0.95V and another at 0.8V. Both are connected to the U3392 component.

Here, Vout = 0.8V is connected to FB2818, which is connected to U3392.

U3392 is also connected to 0.95V.

As a result, 0.95V is forcing current to 0.8V, which is negative current through FB2818.

SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

Renu Vibha — Mon, 03 Aug 2026 05:26:48 GMT

Curious about S-Parameters, Insertion Loss, or Return Loss?

Bring your questions and join our upcoming Cadence Sigrity SI/PI Live Experts Session.

Learn proven analysis techniques, hear practical use cases, and interact directly with Cadence specialists.

Topic - Pre-layout Simulations covering Aurora Workflows, Topology Workbench (Pre-layout), Power SI ERC

Participate here on August 19^th at 7:30-8:30PM IST.

Bring your questions. Leave with answers

Target Impedance Calculation for Multiple Devices on a Shared Power Rail

jillashiva — Thu, 30 Jul 2026 10:46:50 GMT

A common power integrity question is whether nearby devices on the same power rail should be treated as one load or as separate loads when calculating target impedance.

Target impedance is generally calculated as:

Ztarget = ΔV allow / ΔI transient

If multiple devices share the same rail, local PDN path, and decoupling network, the PDN sees the combined current demand. Therefore, the rail-level target impedance should normally be based on the summed worst-case transient current.

Examples

Scenario	Current Used	Example Ripple	Target Impedance
1 A device + 0.1 A device	1.1 A total	50 mV	50 mV / 1.1 A = 45.5 mΩ
Two nearby 1 A devices	2 A total	50 mV	50 mV / 2 A = 25 mΩ
FPGA 4 A + DDR 2 A on same rail	6 A total	27 mV	27 mV / 6 A = 4.5 mΩ

Practical Guideline

Nearby devices on the same rail and decoupling island: use the combined worst-case transient current.
Devices far apart: still use the aggregate rail current, but check local impedance and ripple at each load.
Mutually exclusive activity: use the worst active current only if the assumption is validated.

Key Takeaway

Target impedance is primarily a property of the shared PDN/rail, not of an individual IC. Use the sum of simultaneous transient currents for the rail target, then verify each device locally for acceptable voltage ripple and impedance.

IC Package Electrical Model Generation Using Sigrity

cistheta07 — Thu, 30 Jul 2026 08:22:35 GMT

Hi Experts,

I am currently working on an IC package modeling project where I need to generate an electrical model of the package, including the parasitic effects of bumps, BGA balls, traces, vias, and power/ground planes. The extracted model will be used for broadband signal integrity (SI) analysis, and I may need both SPICE netlist and S-parameter representations.

Could you please advise which Sigrity tool would be most suitable for this application?

Any suggestions or recommendations would be greatly appreciated.

Thank you in advance.

Join us for our next Live Experts Session: PowerSI & S-Parameter Analysis on July 29th 2026

Renu Vibha — Thu, 23 Jul 2026 10:55:31 GMT

Curious about S-Parameter extraction, Insertion Loss, and Return Loss?

Join us here for a live session with Cadence experts and get answers to your toughest Signal Integrity questions.

Wednesday July 29, 2026 at 8:30 PM – 9:30 PM IST

Topics:

S-Parameter Extraction
Insertion Loss Analysis
Return Loss Analysis

Why Join?
Ask questions live
Learn from real-world use cases
Gain practical SI insights
Connect with peers and industry experts

Don't miss this opportunity to engage directly with the experts and discover proven approaches to your SI challenges.

Bring your questions. Leave with answers.

Why Cphy compliance demo simu IL result not pass? only 400mil length

JB202607048610 — Sun, 05 Jul 2026 05:05:11 GMT

Got Questions on Sigrity? Let’s Answer Them—LIVE on Wednesday, June 24th

Renu Vibha — Thu, 18 Jun 2026 13:23:47 GMT

Curious about the latest features? Facing real-world design challenges you’d like to crack faster?

This is a much awaited interactive live session with Cadence experts to get the answers you need—right when you need them.

Join us here on June 24, 2026 at 7:30 – 8:30 PM IST

Topics

PCB & IC Package S-Parameter Model Extraction
PDN Voltage Drop Analysis
High-Speed Design Simulation

This is your opportunity to:

Ask live questions
Learn from real use cases
Exchange insights with peers

Bring your challenges. Share your perspective. Be part of the conversation.

Sigrity: 'Getting Started' to 'Sign Off'

Sumith — Thu, 18 Jun 2026 06:17:27 GMT

As a new Sigrity user, what was the first setup, modeling decision, or workflow change that helped you move from ‘getting started’ to getting meaningful SI/PI results—and what do you wish you had known on day one?

PowerDC Queries

cistheta07 — Tue, 26 May 2026 07:46:03 GMT

Hi everyone,

I’m currently working on IR drop analysis using Cadence Sigrity PowerDC and exploring some of its advanced setup options. As I go through the workflow, I have a few questions related to material definition and thermal analysis.
How can I define a custom material file?
Does PowerDC support IR drop simulation across different temperature points?
What engine is used for thermal analysis in PowerDC?
Can we model active components and include the same in IR drop simulation?

Any guidance or insights would be greatly appreciated.

Sigrity - Tip of the week: How to use multiple IBIS models for LPDDR5X controller (DQ + WCK)

ALLpdf — Fri, 22 May 2026 03:52:53 GMT

Parallel Bus Analysis (PBA) and Topology Workbench allow only one controller block, which can load only one IBIS file at a time.

The simplest approach is to open both IBIS files in a text editor, copy the WCK model block from its IBIS file into the controller’s IBIS file, and then assign the WCK pins to this imported model.

The workaround is to merge both IBIS models into one combined IBIS file. This allows SystemSI/TopXp to read both DQ and WCK models from a single IBIS file while mapping each model to its corresponding pins. Thus, this approach merges the content of both files while keeping them logically separate under different [Model] names.

You can use the following template format:

-----------------------------------------------------------

[IBIS Ver] 5.0
[Comment] Combined IBIS for DQ + WCK

[Component] DDR_Controller
  [Pin]
  1   DQ0     DQ_Model
  2   DQ1     DQ_Model
  3   WCK0    WCK_Model
  ...
[End Component]

[Model] DQ_Model
  ... (contents from the first IBIS file)

[Model] WCK_Model
  ... (contents from the second IBIS file)

--------------------------------------------------------------------

Steps:

Open the DQ IBIS file in a text editor.
Copy the entire WCK model block from the second IBIS file.
Paste it below the DQ model block.
Add a single combined [Component] section with all the pins assigned correctly.
Ensure the following:
- Only one [IBIS Ver] line exists.
- Only one [Component] block exists.
- Each pin references the intended model name.

Once merged, the combined IBIS file can be assigned to the controller block without tool limitations.

PowerDC asi_spd.dll

AC202503029240 — Tue, 28 Apr 2026 18:22:27 GMT

Hi

while loading layout file in PowerDC I'm getting below error

Error: Failed to load asi_spd.dll, check the program directory to find asi_spd.dll

even though the bin folder contains asi_spd.dll

kindly helpt to resolve

thanks in advance

Regards,
Anthony

POWERDC

JL202509104850 — Tue, 21 Apr 2026 06:27:24 GMT

1. Why is the input side copper no show the Delta W data.

Power SI - Query on Retrieving Connected Objects from a Net in PowerSI 2021.1 Using TCL

ABIKRISHNA — Mon, 05 Jan 2026 07:11:48 GMT

Hello Team,

I am currently working on automating a task in PowerSI 2021.1 using a TCL script. I would like to retrieve all objects connected to a given net or any other objects, similar to how we use axlDBGetConnect in Allegro.

Specifically, when I provide a net name, I want the script to return all connected elements such as:

Vias
Components / pins
Traces / clines / shapes

In Allegro, axlDBGetConnect allows us to easily find all elements connected to a given DBID. I am looking for an equivalent or recommended approach in Sigrity PowerSI TCL to obtain this connectivity information.

Could you please let me know:

If there is a direct TCL API or command in PowerSI to query all objects connected to a net
Or, if not, what is the recommended workflow to extract this connectivity data programmatically

downloadind sigrity by university program

YV202508175258 — Sun, 28 Dec 2025 12:25:07 GMT

Hello ,after I sent a request so sigrity I got the following E-mail.

I got to the shopt web page but i dont see the sigrity powerSi link to download.

Is there a direct link I could use?

Thanks.

Thank you for your recent inquiry.

Students and professors have access to academic trials for CFD Simulation, Allegro PCB Design, Microwave Office, OrCAD X Multiphysics Analysis (Clarity, Celsius, Sigrity) available OnCloud through the Cadence University Program. You will need to use your university email address to get the free academic version. Other technologies are not offered at this time.

Go the Cadence University Program page

Select a product and click on ‘Free Access’
Click on ‘Join or log in’ to start today
Login if you already have a Cadence account
If not Click on ‘Create an Academic Account’

Set up OptimizePI

KN202502107649 — Mon, 08 Dec 2025 10:29:29 GMT

Hi everyone,

I’m running a PDN simulation for the VDD rail on my board and I’m not sure how to set up the VRM model and the impedance observation in OptimizePI.

On my board the VDD rail is split into two net names:

VDD_MB: this comes from a connector and gets power from another power board.
After the connector the power goes through resistor R10.
VDD: this is the net after R10 and it powers the load IC (U1).

So the topology is:
external VRM → connector → net VDD_MB → R10 → net VDD → U1.

My questions:

For this topology, should I assign the VRM model to VDD_MB or to VDD in OptimizePI?
For impedance observations, is it enough to create one observation at U1_VDD_GND, or should I also create an observation at the connector/net VDD_MB?

Any suggestions or example setups would be greatly appreciated.

Thank you very much,
Kaydee

How to get the via backdrill layers through TCL script.

ABIKRISHNA — Wed, 19 Nov 2025 06:21:06 GMT

Hello Team,

I am currently working on automating a task in PowerSI 2021.1 using a TCL script. My goal is to remove the backdrill from vias based on a given net name. We are able to retrieve the vias associated with the net, but we are unable to get the details of each via connecting layers using script.

Could you please advise on how to identify the backdrill start and end layers of via through TCL.

Cadence Connect Ahmedabad, India | Join us in Ahmedabad for an exclusive seminar on System-Level Design and Analysis on November 27, 2025

Renu Vibha — Mon, 17 Nov 2025 06:48:25 GMT

Join us in Ahmedabad for an exclusive seminar on System-Level Design and Analysis!

As design complexity grows, engineers face increasing pressure to deliver faster, more accurate results.

This session brings together industry experts to showcase how AI-driven automation, intelligent methodologies, and advanced multiphysics analysis are transforming PCB design and verification.

Why Attend?
Discover smarter ways to manage design complexity
Learn how data-driven automation accelerates productivity
Gain insights into optimizing electrical, thermal, and EM performance

Ahmedabad | November 27, 2025
Register now: https://events.cadence.com/CadenceCONNECT_PCB_Ahmedabad?utm_source=SM&utm_medium=SM&utm_cam…

How to assign a group of BGA pin in OptimizePI

HASAN2024 — Thu, 13 Nov 2025 14:16:25 GMT

Hi there,

I got stuck, with a simulation in OptimisePI,

My board is bit different; it has 4000 BGA pins in bottom and over 500 decaps.

Now , let me give you some examples then it will be easy for you to understand what I want to do.

Power Integrity analysis

Impedance checking

IC Device Power Pin Inductance Analysis

Setup

Frequency 1MHz (default)

VRM not defined

All VDDC caps are shorted

Need to simulate :

BGA pin inductance( Inductance observed at VDDC BGA pins ,BGA pins are defined as IC device.

Let me know how I can make net for this type of BGA pin row,

https://drive.google.com/file/d/1PtezuAY4AOoQTkx9QOZCZwMRaqkof9gE/view?usp=drive_link

BGA pin inductance a polygon is placed over the BGA row and the capacitor package keep-out/ mask is present there.

And most importantly, I don’t know how the engineer has ordered the BGA row with caps, he mentioned in his simulation result like, Row AG-BG/ Row BJ-CJ/ Row CL-DJ, where the caps are considering vertical and horizontally placed in layout. Any axis rotation?

Cadence Connect Hyderabad, India - Register for Futuristic Design Authoring for Integrated Signal, Power, and Thermal Design Session on Nov 25

Renu Vibha — Tue, 11 Nov 2025 10:08:37 GMT

Join us in Hyderabad for an exclusive seminar that dives into the evolving challenges of system-level design and analysis. As design complexity grows, engineers are under pressure to deliver faster, more accurate results without compromising innovation.
This session brings together domain experts to showcase how intelligent design methodologies, AI-driven automation, and advanced multiphysics system analysis are reshaping the way teams approach schematic capture, layout, signal, power, thermal integrity, and electromagnetic simulations.

Why Attend?

Discover smarter ways to manage front-end design complexity and accelerate design intent capture
Learn how data-driven automation is transforming layout productivity and verification cycles
Explore new approaches to signal and power integrity analysis for faster convergence and higher accuracy
Gain practical insights into optimizing design performance across electrical, thermal, and EM domains

Whether you're building next-gen systems or streamlining design cycles, this seminar will equip you with actionable strategies to stay ahead.

Event Details
Date: November 25, 2025
Time: 9:30am – 4:30pm IST
Location: Novotel Hyderabad Convention Centre (HICC), HITEC City, Hyderabad

Sigrity Aurora Create Pin Pairs Greyed out

Don2009 — Mon, 10 Nov 2025 10:49:37 GMT

Hi Everyone,

I am in the middle of learning Sigrity Aurora through an online course and have come across a problem which has brought me to a halt. I am trying to add constraints to an ECSET but it is greyed out.

I am clicking setup>constraints>electrical, right clicking on the net and select Explore Topology which then opens the topology explorer, select the ECSet tab, click Set Topology Constraints, click the green + symbol beside Impedance and when the Create Pin Pair - Impedance window opens it's greyed out.

Any ideas or help on what is causing this and more importantly how to get this sorted is much appreciated.

Thanks everyone!

Issue with Impedance/Reflection Analysis in Sigrity Aurora 23.1

AT202510166839 — Tue, 21 Oct 2025 03:51:25 GMT

Hello Cadence Community,

I am using Sigrity Aurora 23.1 and while performing reflection and impedance analysis, the error log initially showed:

The database version of the design file is not compatible with the Sigrity release version that is currently installed. Refer to the Compatibility Matrix section of the Installation Guide for information on the compatible Sigrity release version.

To resolve this, I installed Hotfix 2, which is compatible with Sigrity Aurora 23.1 and PCB Editor 23.1 base version.

My board design was originally done in Allegro 17.2, so I:

Saved the board in PCB Editor 23.1,
Then opened it in Sigrity Aurora 23.1.

After installing Hotfix 2, while simulating the analysis, the database compatibility issue was resolved, but a new problem arose:

invalid command name "sigrity::selectnet"

The net selection workflow seems to be working as expected, but this message still appears in the log and may be affecting the analysis.

Could someone guide me on:

How to handle this sigrity::selectnet issue in HF2, & complete the simulation.

Any suggestions or workarounds would be highly appreciated.

Thank you!

Anusree T V

Project Engineer

Centre for Development of Advanced Computing

Ciarity PCB Extraction Suite issue 2024

jasonman — Mon, 08 Sep 2025 03:02:43 GMT

Hi Cadence,

i'm Jason

I want to try use "Ciarity PCB Extraction Suite issue 2024" extracted PKG

but always show error

below to

1. E1699 Load w3d mesh data error

2. Internal error 58807 no intersection found between curves

i dont know any idea how to kill it

could you have any suggestion

B.R

Thanks

Jason