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RE: How to include exact 0 Hz (DC) point in PowerSI to avoid low-frequency extrapolation?

AK20250609765 — Tue, 15 Sep 2026 12:20:50 GMT

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Date: Wednesday, September 16, 2026
Time: 8:30 PM - 9:30 PM IST

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How to include exact 0 Hz (DC) point in PowerSI to avoid low-frequency extrapolation?

cistheta07 — Thu, 10 Sep 2026 06:42:54 GMT

Hi Experts,

I am currently working on a high-speed PCB design that requires both Power Integrity (PI) impedance profiling and time-domain transient SPICE simulations. My analysis needs to cover the entire frequency range-from static DC up to several gigahertz.

When I run standard AC S-parameter extractions in Hybrid Solvers, the solver extrapolates data at low frequencies (below 100 kHz down to 0 Hz). As a result, the low-frequency plane resistance ( $R_dc$ ) isn't accurate, which distorts low-frequency die-bump impedance ( $Z_die)$ plots and results in miscalculated bulk decoupling capacitor requirements.

Additionally, if I run transient circuit simulations using these extrapolated models, my SPICE solver often experiences convergence issues due to non-physical DC offsets.

How can I configure PowerSI to include an exact 0 Hz static DC point in my S-parameter extractions so I don't rely on mathematical extrapolation?

Thankyou in advance.

RE: How to include exact 0 Hz (DC) point in PowerSI to avoid low-frequency extrapolation?

AK20250609765 — Tue, 15 Sep 2026 12:17:08 GMT

Hi Cistheta,

Thank you for your question.

When accurate DC-to-high-frequency behavior is required, relying on low-frequency AC extrapolation down to 0 Hz may not provide an accurate DC reference. PowerSI provides a DC–AC fitting feature that uses PowerDC to calculate the static DC solution and incorporates it into the S-parameter model.

To obtain an accurate static 0 Hz reference in PowerSI, enable the Calculate DC point as reference option under:
Tools → Options → Edit Options → Simulation (Advanced) → Field Domain → PowerDC Option

Alternative: Merge Existing DC and AC Models

If you already possess a standalone DC model (from PowerDC or measurements) and a separate high-frequency AC S-parameter model (e.g., starting at ), you do not need to re-run the full EM extraction.

PowerSI provides the Merge DC+Normal data feature, which allows the DC and AC datasets to be combined into a single S-parameter model.

Please let me know if you have any further questions.

Best regards,
Alok

What has been your most challenging Signal Integrity issue in a recent design, and which Sigrity features or workflows proved most valuable in diagnosing and solving it?

Sumith — Thu, 10 Sep 2026 07:18:11 GMT

Automated Layout Validation During PCB/Package Translation in Sigrity & Clarity

cistheta07 — Mon, 17 Aug 2026 06:45:48 GMT

Hello Experts,

Is there a way to perform layout integrity checks during PCB or IC Package translation into the Sigrity/Clarity environment?

Specifically, can the tool automatically detect issues such as floating nodes, short circuits, and open circuits during translation, and provide warnings or mark the error locations? Additionally, is there a TCL command available to enable this validation in workflows?

Thank you.

RE: Automated Layout Validation During PCB/Package Translation in Sigrity & Clarity

AK20250609765 — Thu, 27 Aug 2026 08:14:50 GMT

Hi Cistheta,

Yes. Sigrity and Clarity provide a Layout Validation feature that can automatically perform layout integrity checks during PCB or IC Package translation into the Sigrity/Clarity environment.

When Layout Validation is enabled, the tool automatically runs a comprehensive set of error-checking functions during the translation process and can detect issues such as:

Floating Nodes
Geometry Errors
Short Circuits
Open Circuits

In addition to detecting these issues, the tool can:

Mark error locations directly on the layout
Display warning messages for detected short circuits
Control warning output limits
Ignore specific warnings, such as short circuits between REF_plane and GND nets

The feature can be enabled through:
Tools → Options → Edit Options → Translator → Settings → Layout Validation

Once enabled, validation is performed automatically during the translation of supported databases such as Cadence Allegro (.brd), ODB++, and Gerber designs into the Sigrity/Clarity environment.

For automation workflows, the following TCL command can be used:

sigrity::spdif_option LayoutValidation 1

1 = Enable Layout Validation
0 = Disable Layout Validation

This option acts as a master validation switch, automatically executing the available layout integrity checks and applying the configured error-reporting behavior during translation.

Best regards,
Alok

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

AK20250609765 — Wed, 19 Aug 2026 15:11:35 GMT

Thank you everyone for the great questions and engagement today. We will follow up on pending items shortly and appreciate your participation.

SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

Renu Vibha — Mon, 03 Aug 2026 05:26:48 GMT

Curious about S-Parameters, Insertion Loss, or Return Loss?

Bring your questions and join our upcoming Cadence Sigrity SI/PI Live Experts Session.

Learn proven analysis techniques, hear practical use cases, and interact directly with Cadence specialists.

Topic - Pre-layout Simulations covering Aurora Workflows, Topology Workbench (Pre-layout), Power SI ERC

Participate here on August 19^th at 7:30-8:30PM IST.

Bring your questions. Leave with answers

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

AK20250609765 — Wed, 19 Aug 2026 15:09:13 GMT

Thank you for the question. When a channel fails compliance testing, engineers typically investigate insertion loss, return loss, crosstalk, ISI, eye margin, and SNR. The goal is to determine whether the failure is caused by excessive channel attenuation, reflections from impedance discontinuities, coupling from aggressor nets, or degraded receiver margin. In practice, S21 (insertion loss), S11 (return loss), crosstalk, eye opening, and SNR are among the most important indicators used to isolate the root cause of a compliance failure.

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

AK20250609765 — Wed, 19 Aug 2026 15:04:06 GMT

The handoff typically breaks down when the logical connectivity used during topology creation no longer matches the physical implementation. Pin-name mismatches, component-definition differences, or connectivity mapping issues can prevent correct constraint transfer, forcing manual re-assignment of routing constraints in the layout flow. Maintaining consistent schematic-to-layout mapping is key.

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

CF202606104231 — Wed, 19 Aug 2026 14:57:12 GMT

When a channel fails compliance testing , what SI metrics is typically investigated?

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

EDAHut — Wed, 19 Aug 2026 14:54:55 GMT

During pre layout engineer creates a tuned LPDDR4 memory topology with specific termination resistors using generic schematic nodes … when transferring this to physical layout , mismatching pin names between the schematic symbols and the actual layout footprints break the net connectivity mapping in Aurora .. this completely resets the constraint manager rules, forcing the layout team to manually reassign routing constraints from scratch

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

AK20250609765 — Wed, 19 Aug 2026 14:54:39 GMT

Thank you for the question.

AI servers and high-performance computing (HPC) systems introduce several unique challenges for signal integrity (SI) engineers:

Heterogeneous Architectures: The integration of various processing units, such as CPUs, GPUs, and AI processors, requires careful management of signal integrity across different components, which can complicate design and validation processes.
High-Speed Signaling: The demand for high-speed data transfer increases the risk of signal integrity issues, including crosstalk, attenuation, and reflections. Engineers must implement advanced techniques to mitigate these effects.
Memory Bandwidth Limitations: The "memory wall" phenomenon, where memory bandwidth does not scale with the number of cores, poses challenges in ensuring that data can be efficiently accessed and processed without bottlenecks.
Thermal Management: Increased power consumption from high-performance components generates heat, which can affect signal integrity. Engineers must design effective cooling solutions to maintain optimal operating conditions.
Electromagnetic Interference (EMI): The complexity of modern AI workloads can lead to increased EMI, necessitating careful design to minimize interference and ensure compliance with regulatory standards.
Complex Routing Constraints: The intricate layouts required for high-speed signals on PCBs can lead to routing challenges, requiring innovative design strategies to maintain signal integrity.
Modular Designs: The shift towards disaggregated architectures and modular designs, facilitated by standards like UCIe, requires SI engineers to adapt to new connectivity standards and ensure compatibility across diverse components.

Addressing these challenges is crucial for the successful deployment of AI servers and HPC systems, ensuring reliable performance and efficiency in demanding environments.

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

AK20250609765 — Wed, 19 Aug 2026 14:50:46 GMT

Thank you for the question. Before running detailed SI simulations, I would recommend using the PowerSI ERC - Trace Imp/Cpl/Ref Check workflow. While impedance may be within specification, SI issues can still arise from excessive coupling, missing or discontinuous reference planes, and localized routing violations. The ERC workflow automatically checks these conditions and reports violations through detailed tables and layout overlays, making it easy to identify the exact trace segments responsible for potential SI degradation. This allows layout issues to be corrected early, reducing simulation iterations and improving overall design quality.

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

cistheta07 — Wed, 19 Aug 2026 14:45:06 GMT

In a high-speed DDR or SerDes design, impedance may be within specification, yet signal integrity issues can still occur. What layout-related factors should be investigated to identify the root cause before running detailed simulations?

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

EDAHut — Wed, 19 Aug 2026 14:44:47 GMT

Where does the handoff from schematic driven topologies to physical layout in Cadence Sigrity Aurora break down the most ?

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

CF202606104231 — Wed, 19 Aug 2026 14:39:45 GMT

What new challenged does AI servers and high performance computing systems present for SI Engineers. Can you throw some light

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

EDAHut — Wed, 19 Aug 2026 14:39:03 GMT

Helpful thanks

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

AK20250609765 — Wed, 19 Aug 2026 14:30:45 GMT

Thank you for the question.

A typical example is a high-speed PCIe or SerDes channel where the eye diagram fails to meet the required margin. By analyzing S21 (insertion loss), engineers can identify excessive channel attenuation at higher frequencies. The root cause is often excessive trace length, via discontinuities, connectors, or a high-loss dielectric material.
After optimizing the channel geometry or selecting a lower-loss stackup, the insertion loss improves, leading to better signal quality and improved eye opening. Therefore, S21 is commonly used to verify that the channel meets its loss budget and can support the target data rate before manufacturing.

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

AK20250609765 — Wed, 19 Aug 2026 14:26:08 GMT

Thank you for the question.
To maintain the validity of pre-layout signal integrity (SI) results when the PCB stackup changes during the design cycle, follow these steps:

Correctly Model Devices: Ensure that all devices are accurately modeled. This is crucial for the validity of pre-layout simulations.
Reassess Design Constraints: After any changes to the stackup, reassess the design constraints that were initially applied. This helps in identifying any new requirements or adjustments needed.
Utilize Model Assignment Utility: Use the Model Assignment utility to associate device models with schematic components. This ensures that the updated stackup is reflected in the simulations.
Iterative Analysis: Conduct iterative analyses after stackup modifications. This allows for adjustments based on the new stackup configuration and ensures that the results remain relevant.
Documentation and Archiving: Keep detailed records of all changes and their impacts on SI results. This aids in tracking the evolution of the design and understanding the implications of stackup changes.

By following these practices, you can ensure that your pre-layout SI results remain valid and reliable throughout the design process

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

CF202606104231 — Wed, 19 Aug 2026 14:21:22 GMT

Can you share example where analysing insertion loss (s21) helped identify and resolve a signal integrity in a high speed design?

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

EDAHut — Wed, 19 Aug 2026 14:18:32 GMT

Thank you for hosting. One question… how to prevent per layout model from giving a false sense of security when stack up definitions change mid stream ?

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

AK20250609765 — Wed, 19 Aug 2026 14:15:48 GMT

Thank you for the question. In real-world PCB and package design, S-parameters are used to characterize how signals propagate through interconnects, while return loss (S11) is used to measure how much signal energy is reflected back due to impedance discontinuities.

For example, in a DDR5 channel, engineers can extract S-parameters for the traces, vias, connectors, and package and evaluate return loss across the operating frequency range. If excessive reflections are identified, the routing or via structure can be optimized before fabrication. This helps reduce SI issues during hardware bring-up and increases the likelihood of a successful first prototype spin.

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

AK20250609765 — Wed, 19 Aug 2026 14:08:53 GMT

To get us started, one common question we often hear is: How can we identify potential SI/PI issues early in the design cycle, before the board goes to fabrication?
Here’s a quick perspective: Cadence Sigrity Aurora is a signal and power integrity (SI/PI) analysis solution tightly integrated into the Allegro PCB design environment. Its In-Design Analysis (IDA) capabilities enable engineers to perform analysis directly within the PCB environment and visualize the impact of design changes in real time. Aurora also provides layout analysis workflows for evaluating key concerns such as impedance, coupling, crosstalk, return paths, reflections, and IR drop. In addition, Sigrity Topology Explorer enables early what-if analysis to evaluate different design scenarios before committing to the final PCB implementation. By identifying potential SI/PI-related layout issues early, engineers can make informed design decisions and help avoid potentially expensive board respins. Has anyone encountered a similar challenge in their designs?

RE: SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

CF202606104231 — Wed, 19 Aug 2026 14:08:41 GMT

In practical PCB or package designs , how are S-parameters and return loss measurements used ? Give me a real world example to validate performance before a product goes into manufacturing?