https://community.cadence.com/cadence_technology_forums/system-analysis/en-USTelligent Community 12https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24th/1408745Mon, 22 Jun 2026 08:28:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:678a1737-bd31-4897-84db-d7b4f4f8eeacRenu Vibha2 days to go! If you’re working with Cadence Sigrity tools or exploring signal and power integrity concepts, this session is a great opportunity to get your queries clarified in real time. Bring your questions- we'll bring the experts.https://community.cadence.com/cadence_technology_forums/system-analysis/f/celsius-thermal-solver/66088/multiple-celisus-toolsFri, 19 Jun 2026 09:38:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c7d0ca70-69e3-464c-b105-0765b8af6870TT202605198653When you launch Celsius Studio, there are 5 different tools. What's the purpose of each of them?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24thThu, 18 Jun 2026 13:23:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:110ade6d-2f58-46f3-92d8-a70f3aa58a15Renu VibhaCurious about the latest features? Facing real-world design challenges you’d like to crack faster? This is a much awaited interactive live session with Cadence experts to get the answers you need—right when you need them. Join us here on June 24, 2026 at 7:30 – 8:30 PM IST Topics PCB & IC Package S-Parameter Model Extraction PDN Voltage Drop Analysis High-Speed Design Simulation This is your opportunity to: Ask live questions Learn from real use cases Exchange insights with peers Bring your challenges. Share your perspective. Be part of the conversation.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66085/sigrity-getting-started-to-sign-offThu, 18 Jun 2026 06:17:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:22c831d9-7ad7-4a7d-b873-f42cff157853SumithAs a new Sigrity user, what was the first setup, modeling decision, or workflow change that helped you move from ‘getting started’ to getting meaningful SI/PI results—and what do you wish you had known on day one?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66011/powerdc-queries/1408513Sun, 31 May 2026 18:47:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c5d5630f-367c-4388-9af1-c0c993b49156SumithPowerDC supports IR drop simulation across various temperature points, but it requires temperature-dependent material definitions to be set up and assigned to all objects in the database. Please note that non-linear characteristics of active components might not be accurately captured in the simulation. However, you can define the power dissipation values for these components to enable thermal analysis. Could you please clarify your objectives regarding the active components in this simulation?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66011/powerdc-queries/1408499Fri, 29 May 2026 04:28:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:33483da3-d81d-478d-88a7-9a4f58581e79cistheta07Hi Shiva Shankar and Community, Thank you for sharing your insights. It is good to know that custom materials can be defined by the Material Manager in PowerDC. Could you please guide me through the steps required to define a custom material? At present, my primary focus is on correlating electrical results across different temperature conditions. Going forward, I would also like to explore the electro-thermal aspects of the analysis and understand how thermal distribution impacts the IR-drop behavior of the power delivery network. I would also appreciate it if other experts in the community could share their insights or recommendations related to the other questions mentioned above.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66011/powerdc-queries/1408496Tue, 26 May 2026 08:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6b2203d5-6a15-4bdb-99f0-4a827efcdbbeShivaShankarMHey cistheta07, Interesting set of questions — I’ve run into some of these while working with PowerDC as well For the material part, you can define custom materials through the Material Manager in the stackup setup. It also allows you to assign conductivity values at different temperature points, so you can explore how IR drop behaves with temperature variations. Out of curiosity — are you trying to correlate electrical results at different temperatures, or planning to look at electro-thermal effects as well? Thanks, Shiva Shankar Mhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66011/powerdc-queriesTue, 26 May 2026 07:46:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b2c5dac8-b2fb-425d-8570-5e783f4c35dccistheta07Hi everyone, I’m currently working on IR drop analysis using Cadence Sigrity PowerDC and exploring some of its advanced setup options. As I go through the workflow, I have a few questions related to material definition and thermal analysis. How can I define a custom material file? Does PowerDC support IR drop simulation across different temperature points? What engine is used for thermal analysis in PowerDC? Can we model active components and include the same in IR drop simulation? Any guidance or insights would be greatly appreciated.SigrityPowerDChttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66008/sigrity---tip-of-the-week-how-to-use-multiple-ibis-models-for-lpddr5x-controller-dq-wckFri, 22 May 2026 03:52:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:36ee38d4-ab65-4fdd-9b0e-c1d3872ccfe4ALLpdfParallel Bus Analysis (PBA) and Topology Workbench allow only one controller block , which can load only one IBIS file at a time . The simplest approach is to open both IBIS files in a text editor, copy the WCK model block from its IBIS file into the controller’s IBIS file, and then assign the WCK pins to this imported model. The workaround is to merge both IBIS models into one combined IBIS file . This allows SystemSI/ TopXp to read both DQ and WCK models from a single IBIS file while mapping each model to its corresponding pins. Thus, this approach merges the content of both files while keeping them logically separate under different [Model] names. You can use the following template format: ----------------------------------------------------------- [IBIS Ver] 5.0 [Comment] Combined IBIS for DQ + WCK [Component] DDR_Controller [Pin] 1 DQ0 DQ_Model 2 DQ1 DQ_Model 3 WCK0 WCK_Model ... [End Component] [Model] DQ_Model ... (contents from the first IBIS file) [Model] WCK_Model ... (contents from the second IBIS file) -------------------------------------------------------------------- Steps: Open the DQ IBIS file in a text editor. Copy the entire WCK model block from the second IBIS file. Paste it below the DQ model block. Add a single combined [Component] section with all the pins assigned correctly. Ensure the following: Only one [IBIS Ver] line exists. Only one [Component] block exists. Each pin references the intended model name. Once merged, the combined IBIS file can be assigned to the controller block without tool limitations.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/65941/powerdc/1408342Fri, 24 Apr 2026 15:04:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:da69c4d6-1d19-4827-8cf0-3141395e5a2ejillashivaIt seems the query is incomplete. Please elaborate with additional details and resubmit your question so we can assist you further. -Shiva Prasad Jillahttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/65941/powerdcTue, 21 Apr 2026 06:27:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0f7362cb-fc73-4589-b369-e9d5c6cf231dJL2025091048501. Why is the input side copper no show the Delta W data.PowerDChttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/65614/power-si---query-on-retrieving-connected-objects-from-a-net-in-powersi-2021-1-using-tcl/1407532Mon, 19 Jan 2026 05:13:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f2a61114-6f49-49d1-b7d5-85219d37d7eeABIKRISHNAHello Shiva Shankar M, Thank you for your response. We tried this method, but unfortunately it works only in PowerSI 25.1 . In PowerSI 2021.1 , the command does not seem to be available / does not return the required connectivity information. Our actual requirement is the following: The user provides one or more net names From the given nets, we need to identify all connected vias From those vias, we need to detect backdrilled vias Finally, we need to remove the backdrill irrespective of topology (point-to-point, multi-drop, plane connections, etc.) Since sigrity::showObjectsofNets is not supported in 2021.1, could you please advise: Is there any alternative TCL API in PowerSI 2021.1 to retrieve vias connected to a given net? Is there a recommended workflow in older PowerSI versions to identify backdrilled vias programmatically ? Are there any examples or internal commands available in 2021.1 for backdrill detection/removal? Any guidance specific to PowerSI 2021.1 would be greatly appreciated. Thanks and regards, Abikrishna.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/65614/power-si---query-on-retrieving-connected-objects-from-a-net-in-powersi-2021-1-using-tcl/1407398Mon, 05 Jan 2026 07:44:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6aa63291-3725-4b37-9a37-1ffece518c28ShivaShankarMHi ABIKRISHNA, You can try below TCL to get details like Trace, via, Node, components, shapes etc., for a particular net. sigrity::showObjectsofNets -nets { } {!} I've tried it in PowerSI v25.1 release and got expected results, so you can try it in v21.1 release to see how it goes. Thanks, Shiva Shankar Mhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/65614/power-si---query-on-retrieving-connected-objects-from-a-net-in-powersi-2021-1-using-tclMon, 05 Jan 2026 07:11:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:bb423311-8d5b-4590-a569-d258c25c467aABIKRISHNAHello Team, I am currently working on automating a task in PowerSI 2021.1 using a TCL script . I would like to retrieve all objects connected to a given net or any other objects , similar to how we use axlDBGetConnect in Allegro . Specifically, when I provide a net name , I want the script to return all connected elements such as: Vias Components / pins Traces / clines / shapes In Allegro, axlDBGetConnect allows us to easily find all elements connected to a given DBID. I am looking for an equivalent or recommended approach in Sigrity PowerSI TCL to obtain this connectivity information. Could you please let me know: If there is a direct TCL API or command in PowerSI to query all objects connected to a net Or, if not, what is the recommended workflow to extract this connectivity data programmaticallyPowerSIhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/65603/downloadind-sigrity-by-university-program/1407389Fri, 02 Jan 2026 10:37:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:82aa39a5-31f7-4648-840a-95b571f03c70jillashivaThe oncloud Web page give you access to use the software directly , you do not need to download or Install .. It is ready for you ..and you can get started with the simulations ..you can find the Power SI under the Multiphysics Analysis suitehttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/65603/downloadind-sigrity-by-university-programSun, 28 Dec 2025 12:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6856f779-d147-495d-b1c7-ee77233e8ef6YV202508175258Hello ,after I sent a request so sigrity I got the following E-mail. I got to the shopt web page but i dont see the sigrity powerSi link to download. Is there a direct link I could use? Thanks. Thank you for your recent inquiry. Students and professors have access to academic trials for CFD Simulation, Allegro PCB Design, Microwave Office, OrCAD X Multiphysics Analysis (Clarity, Celsius, Sigrity ) available OnCloud through the Cadence University Program. You will need to use your university email address to get the free academic version. Other technologies are not offered at this time. Go the Cadence University Program page Select a product and click on ‘Free Access’ Click on ‘Join or log in’ to start today Login if you already have a Cadence account If not Click on ‘Create an Academic Account’https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/65546/set-up-optimizepi/1407252Tue, 09 Dec 2025 02:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:398981d0-97f3-483f-a5bf-b940f94e7e84KN202502107649Thank you very much Sumith, Topology External power board provides VDD through a connector J5 on my board. Net from connector is called VDD_MB . From J5 the power goes through two resistors R10(DCR ≈ 0.2 mΩ each) to the net VDD . Net VDD powers the main IC U1 . So the path is: external VRM → J5 (VDD_MB) → R101/R102 → VDD → U1. OptimizePI setup (follow your guild line) In Net Manager / P-G classification wizard, both VDD_MB and VDD are classified as PowerNets , GND as GroundNet. In Define VRM Models , I created a VRM model and assigned: Power net = VDD_MB Return net = GND In Impedance Observations , I created two observation points: J5_VDD_MB_GND U1_VDD_GND Analysis type = What-If, frequency range 100 kHz – 1 GHz. Problem / plot The self-impedance at J5_VDD_MB_GND (red curve) is flat and very low (~1 mΩ) across the whole band, which looks like the VRM impedance – this seems correct. But the self-impedance at U1_VDD_GND (blue curve) starts at very high impedance (~10³ Ω) at low frequency and then decreases with 1/ω, with a resonance dip around a few hundred MHz. This shape looks like “no VRM connected, only planes + decaps” . In other words, from the U1 node OptimizePI appears not to “see” the VRM at J5, even though in the physical design they are connected through R10 and I can simulate DC IR drop in PowerDC. Question What is the correct way to set up the VRM and nets so that the VRM at VDD_MB is seen from the load node U1_VDD_GND ? Do I need to do anything special in Select Nets / PowerTree in this older (19.0) OptimizePI flow to make VDD_MB and VDD part of the same rail? Could component filtering be removing R101/R102 or otherwise breaking the connection between VDD_MB and VDD in the OptimizePI circuit?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/65546/set-up-optimizepi/1407249Mon, 08 Dec 2025 22:35:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8466c1cc-d955-4033-9f24-b5ae58dcf7f4KN202502107649Thank you very much @Sumith Topology External power board provides VDD through a connector J5 on my board. Net from connector is called VDD_MB . From J5 the power goes through two resistors R10(DCR ≈ 0.2 mΩ each) to the net VDD . Net VDD powers the main IC U1 . So the path is: external VRM → J5 (VDD_MB) → R101/R102 → VDD → U1. OptimizePI setup (follow your guild line) In Net Manager / P-G classification wizard, both VDD_MB and VDD are classified as PowerNets , GND as GroundNet. In Define VRM Models , I created a VRM model and assigned: Power net = VDD_MB Return net = GND In Impedance Observations , I created two observation points: J5_VDD_MB_GND U1_VDD_GND Analysis type = What-If, frequency range 100 kHz – 1 GHz. Problem / plot The self-impedance at J5_VDD_MB_GND (red curve) is flat and very low (~1 mΩ) across the whole band, which looks like the VRM impedance – this seems correct. But the self-impedance at U1_VDD_GND (blue curve) starts at very high impedance (~10³ Ω) at low frequency and then decreases with 1/ω, with a resonance dip around a few hundred MHz. This shape looks like “no VRM connected, only planes + decaps” . In other words, from the U1 node OptimizePI appears not to “see” the VRM at J5, even though in the physical design they are connected through R10 and I can simulate DC IR drop in PowerDC. Question What is the correct way to set up the VRM and nets so that the VRM at VDD_MB is seen from the load node U1_VDD_GND ? Do I need to do anything special in Select Nets / PowerTree in this older (19.0) OptimizePI flow to make VDD_MB and VDD part of the same rail? Could component filtering be removing R101/R102 or otherwise breaking the connection between VDD_MB and VDD in the OptimizePI circuit?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/65546/set-up-optimizepi/1407248Mon, 08 Dec 2025 22:31:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:73cc2751-9fc3-4827-ad74-f9096b6be1c0KN202502107649Hi Sumith Tool / version Sigrity 19.0, OptimizePI flow Board has been used in PowerDC already and DC path is correct. Topology External power board provides VDD through a connector J5 on my board. Net from connector is called VDD_MB . From J5 the power goes through two resistors R10 (DCR ≈ 0.2 mΩ each) to the net VDD . Net VDD powers the main IC U1 . So the path is: external VRM → J5 (VDD_MB) → R101/R102 → VDD → U1. OptimizePI setup (follow your guideline) In Net Manager / P-G classification wizard, both VDD_MB and VDD are classified as PowerNets , GND as GroundNet. In Define VRM Models , I created a VRM model and assigned: Power net = VDD_MB Return net = GND In Impedance Observations , I created two observation points: J5_VDD_MB_GND U1_VDD_GND (Model Name = @Open@) Analysis type = What-If, frequency range 100 kHz – 1 GHz. Problem / plot The self-impedance at J5_VDD_MB_GND (red curve) is flat and very low (~1 mΩ) across the whole band, which looks like the VRM impedance – this seems correct. But the self-impedance at U1_VDD_GND (blue curve) starts at very high impedance (~10³ Ω) at low frequency and then decreases with 1/ω, with a resonance dip around a few hundred MHz. This shape looks like “no VRM connected, only planes + decaps” . In other words, from the U1 node OptimizePI appears not to “see” the VRM at J5, even though in the physical design they are connected through R101/R102 and I can simulate DC IR drop in PowerDC. Question What is the correct way to set up the VRM and nets so that the VRM at VDD_MB is seen from the load node U1_VDD_GND ? Do I need to do anything special in Select Nets / PowerTree in this older (19.0) OptimizePI flow to make VDD_MB and VDD part of the same rail? Could component filtering be removing R101/R102 or otherwise breaking the connection between VDD_MB and VDD in the OptimizePI circuit?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/65546/set-up-optimizepi/1407247Mon, 08 Dec 2025 22:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:aa2dd7d8-bcd8-48c6-ac6f-34e04d245301KN202502107649Hi Sumith Tool / version Sigrity 19.0, OptimizePI flow Board has been used in PowerDC already and DC path is correct. Topology External power board provides VDD through a connector J5 on my board. Net from connector is called VDD_MB . From J5 the power goes through two resistors R10 (DCR ≈ 0.2 mΩ each) to the net VDD . Net VDD powers the main IC U1 . So the path is: external VRM → J5 (VDD_MB) → R101/R102 → VDD → U1. OptimizePI setup (follow your guideline) In Net Manager / P-G classification wizard, both VDD_MB and VDD are classified as PowerNets , GND as GroundNet. In Define VRM Models , I created a VRM model and assigned: Power net = VDD_MB Return net = GND In Impedance Observations , I created two observation points: J5_VDD_MB_GND U1_VDD_GND (Model Name = @Open@) Analysis type = What-If, frequency range 100 kHz – 1 GHz. Problem / plot The self-impedance at J5_VDD_MB_GND (red curve) is flat and very low (~1 mΩ) across the whole band, which looks like the VRM impedance – this seems correct. But the self-impedance at U1_VDD_GND (blue curve) starts at very high impedance (~10³ Ω) at low frequency and then decreases with 1/ω, with a resonance dip around a few hundred MHz. This shape looks like “no VRM connected, only planes + decaps” . In other words, from the U1 node OptimizePI appears not to “see” the VRM at J5, even though in the physical design they are connected through R101/R102 and I can simulate DC IR drop in PowerDC. Question What is the correct way to set up the VRM and nets so that the VRM at VDD_MB is seen from the load node U1_VDD_GND ? Do I need to do anything special in Select Nets / PowerTree in this older (19.0) OptimizePI flow to make VDD_MB and VDD part of the same rail? Could component filtering be removing R101/R102 or otherwise breaking the connection between VDD_MB and VDD in the OptimizePI circuit?