https://community.cadence.com/cadence_technology_forums/system-analysis/en-USTelligent Community 12https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66133/why-cphy-compliance-demo-simu-il-result-not-pass-only-400mil-length/1408846Mon, 06 Jul 2026 14:35:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a3e7a4af-12ad-4800-944f-5a68e88bdcf0JB202607048610Even if use Standard Channel ,the Compliance DIFF IL value still Unreliable。Because use tools S Parameter Extract Result very smallhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66133/why-cphy-compliance-demo-simu-il-result-not-pass-only-400mil-length/1408842Mon, 06 Jul 2026 12:34:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:98facb39-781c-4473-b0d1-904e7b5481aeSumithYou can choose either the Standard or Long Channel Insertion Loss option in Compliance Check.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66133/why-cphy-compliance-demo-simu-il-result-not-pass-only-400mil-lengthSun, 05 Jul 2026 05:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9f9a9f58-4faa-474e-ae2c-14706a6d05c4JB202607048610https://community.cadence.com/cadence_technology_forums/system-analysis/f/clarity-3d-solver/66127/setting-up-and-simulating-rigid-flex-designs-in-powersi-from-odb-importsThu, 02 Jul 2026 06:36:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e25c448c-5c3f-4647-90b4-111d2d58efffALLpdfThe most robust and recommended approach is ODB++ > Allegro > PowerSI Workflow . Steps: Import the ODB++ file into Allegro . Verify and configure: Rigid‑Flex zones Stackups for rigid and flex regions Save the design as an Allegro .brd file . Import the .brd file into PowerSI for simulation. This workflow (ODB++ > .brd > .spd) is considered more stable and reliable especially for complex Rigid‑Flex designs.https://community.cadence.com/cadence_technology_forums/system-analysis/f/celsius-thermal-solver/66114/importing-icepak-model-into-celsius-ecMon, 29 Jun 2026 17:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:75c15f4c-b5fc-4d4b-bc3b-f69aabeeb56cNS1170Celsius EC Solver can import Icepak models upto V14.5 or earlier. To import the model, click on Import and select TZR . The models after V14.5 are encrypted and cannot be imported in Celsius EC directly. To import Icepak model, it is recommended to export the model as ECXML file. ECXML is neutral format thermal model that can be imported in Celsius EC. To import ECXML file, go to Import ribbon and click ECXML to import an ECXML file into Celsius EC Solver as a new model, a component or an assembly.https://community.cadence.com/cadence_technology_forums/system-analysis/f/celsius-thermal-solver/66088/multiple-celisus-tools/1408806Mon, 29 Jun 2026 17:32:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6046fbe8-21a4-4bbe-b517-b68e4ab93b58NS1170Sharing short introduction of each of these tools: 1. Celsius Layout - For Layered structures (PCBs, Package substrates). Used for Electro-thermal Cosimulation. 2. Celsius 3D WorkBench - For full 3D systems. Can be used for Electro-thermal Cosiumulation and stress&warpage simulation. 3. Celsius 3DIC - For stacked-die systems. 4. Celsius EC - Used for CFD analysis for full 3D solid object systems. 5. Celsius Thermal Network - For large-scale electronic systems. For more details, refer to ask.cadence.comhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24th/1408783Wed, 24 Jun 2026 15:09:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:bed168d2-510e-4468-a60e-17fd2b986708EDA StarThat make sa lot of sense. I actually facd a similar issue recently on a dense board where the simulation wouldn't converge because of a tight current bottleneck near a small power pin. I cudnot widen the copper trace because of layout space, and adding more vias wasn't possible due to routing rules. In a tough spot like that where you can't just 'add more copper,' what is the next best trick in PowerDC to help a designer find a creative way out?"https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24th/1408782Wed, 24 Jun 2026 15:07:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8faed83d-b232-4bd8-844d-eb778932c008ShivaShankarMThank you everyone for the great questions and engagement today. We will follow up on pending items shortly and appreciate your participation. Regards, Shiva Shankar Mhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24th/1408781Wed, 24 Jun 2026 15:06:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8b6ab1bc-1ade-4468-85a4-72b7a8effff0ShivaShankarMIf an electro-thermal simulation fails to converge, it's often an indication of a real design issue rather than just a simulation issue. The first things you should investigate are current-density hotspots, excessive IR drop, localized temperature rise, and PDN bottlenecks. Typical fixes include: Increasing copper width/thickness Adding more vias or parallel current paths Improving cooling (thermal vias, heatsinks, airflow) Reducing load concentration and spreading current more evenly In PowerDC, focus on regions showing the highest current density, temperature rise, and resistance increase, as these are usually the root causes preventing convergence.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24th/1408780Wed, 24 Jun 2026 15:02:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e20ed741-7bea-46c9-9f98-f1eab0afd6eeEDA StarHmmm...This helps... Thank you !https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24th/1408779Wed, 24 Jun 2026 15:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:fda266dd-ea24-48ef-a946-68d34c58cbcfShivaShankarMGood question, EDA Star! Cadence provides a Clarity 3D Cut-and-Stitch flow, where EM-critical regions (such as BGA breakouts, vias, package escapes, etc.) can be solved using the Clarity 3D FEM solver, while the remaining layout is solved using PowerSI's hybrid extraction engine. To avoid introducing artificial discontinuities, the Clarity and PowerSI regions are stitched together at consistent electrical boundaries with matching signal/reference definitions. The stitched model is then validated using metrics such as TDR continuity, impedance correlation, and IL/RL consistency before performing system-level simulations. The resulting composite model can be analyzed in Topology Workbench/SystemSI for eye diagrams, jitter, SSN/PDN analysis, timing margin evaluation, and SerDes compliance verification.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24th/1408778Wed, 24 Jun 2026 14:56:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c8b68982-6e17-42ad-a35e-6ab017ee6b7aEDA StarTHank you... Sometimes in high-current designs, the loop keeps heating up copper, the resistance keeps rising, and the simulation fails to converge (it errors out). When PowerDC fails to reach equilibrium, what are the best design steps to fix this thermal runaway issue?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24th/1408777Wed, 24 Jun 2026 14:53:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:60b93a4c-b14f-4014-a32c-110768ca372fShivaShankarMIn Sigrity PowerDC, electrical and thermal effects are analyzed using its electro-thermal (ET) simulation capability, which is essential because temperature directly impacts copper resistance and hence IR drop. PowerDC first solves the DC current distribution and IR drop, computes the resulting Joule heating, updates the copper conductivity/resistance based on temperature, and then re-solves the electrical network. This iterative process continues until both temperature and voltage results converge. The key outputs are temperature hotspots, current density, copper temperature rise, resistance increase, and the resulting IR drop/voltage at sinks, allowing you to directly quantify how self-heating impacts power delivery.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24th/1408776Wed, 24 Jun 2026 14:46:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b0eb05aa-aadf-43ed-9af3-83a60d1a09d4EDA StarOK. Since you recommended a hybrid flow combining PowerSI and Clarity 3D, how do you handle the port-mapping and reference-ground alignment when stitching the 3D Clarity via-models back into the PowerSI layout to ensure no artificial discontinuities are introduced in SystemSI?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24th/1408775Wed, 24 Jun 2026 14:45:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9f0c1e8c-48ba-48b7-a322-53daa3fc1b2fShivaShankarMEngineers use field solvers because real designs involve complex 3D electromagnetic interactions, coupling, and PDN effects that simple rule-based calculations cannot accurately capture.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24th/1408774Wed, 24 Jun 2026 14:44:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:da6520d8-c683-4fe3-b445-ffa6408c6e29EDA StarAlso..... In Cadence Sigrity PowerDC, how do we run the electrical and thermal simulation together to see how heat changes the copper resistance and affects the voltage drop?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24th/1408773Wed, 24 Jun 2026 14:41:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1d22d6a3-6ac9-4152-832b-4581d910f98dShivaShankarMThank you for the question. Based on what you’ve shared, f or DDR5 SSN analysis, it’s best to balance full-wave EM and hybrid extraction rather than treating them as alternatives. use Clarity 3D for EM-critical regions (BGA breakouts, vias, package escapes, return-path discontinuities) and PowerSI/SystemSI for the full package-board model after correlating against a representative full-wave subset. To ensure the PDN is not degrading SI, monitor PDN impedance vs target impedance, anti-resonance peaks, VDDQ/VSS ripple, eye height/width, DQ–DQS timing margins, setup/hold margins, jitter, and SSN-induced power/ground bounce. Model validation should also include TDR, IL/RL correlation, passivity, and causality checks.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24th/1408772Wed, 24 Jun 2026 14:37:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:fdc257b8-74a7-4502-9305-5fdf3eea332bCF202606104231Why do Engineers use field - solvers like PowerSI instead of rule-of-thumb calculations?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24th/1408771Wed, 24 Jun 2026 14:33:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b2d16d31-40af-48dc-93c4-423200fd49d2EDA StarWhen performing simultaneous switching noise (SSN) analysis for high-speed memory interfaces like DDR5 using Cadence Sigrity, how do you accurately balance the trade-off between using a full-wave 3D EM extraction versus a hybrid approach (like Sigrity PowerSI) for the package-board composite model, and what specific metrics do you look for to validate that your power delivery network (PDN) isn't degrading signal integrity?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24th/1408770Wed, 24 Jun 2026 14:10:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e6d7f290-4777-4967-97f5-45b10488ea6bShivaShankarMTo get us started, here's a common question: "How much spacing is enough to reduce crosstalk between high-speed traces?" A quick perspective: There isn't a single rule that works for every design. Stackup, trace geometry, rise time, and reference planes all influence coupling behavior. What crosstalk challenges have you faced in your projects?