https://community.cadence.com/cadence_technology_forums/system-analysis/en-USTelligent Community 13https://community.cadence.com/cadence_technology_forums/system-analysis/f/clarity-3d-solver/66297/join-us-on-wednesday-sep-16th-2026-for-our-next-live-ask-me-anything-session-on-trusting-simulation-clarity-at-50-ghz-and-beyond-and-discover-how-to-achieve-accurate-reliable-results-for-next-generation-high-speed-designs/1409296Thu, 10 Sep 2026 09:36:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:58939b5d-d1fc-4412-8a9b-8dfccdedc901Renu VibhaThank you for your active participation in our past sessions. We hope the discussions were helpful and that we were able to provide timely responses to your questions. As part of our continued commitment to supporting you, our next session is scheduled for September 16 , and we would be delighted to have you join us at 8:30 PM - 9:30 PM IST Topic: Trusting Simulation Clarity at 50 GHz and Beyond .https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66325/what-has-been-your-most-challenging-signal-integrity-issue-in-a-recent-design-and-which-sigrity-features-or-workflows-proved-most-valuable-in-diagnosing-and-solving-itThu, 10 Sep 2026 07:18:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:202de8f3-201e-4cb0-b7f7-d47f079c8368Sumithhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66324/how-to-include-exact-0-hz-dc-point-in-powersi-to-avoid-low-frequency-extrapolationThu, 10 Sep 2026 06:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7312cd88-21ce-4983-9677-50b9f7f20079cistheta07Hi Experts, I am currently working on a high-speed PCB design that requires both Power Integrity (PI) impedance profiling and time-domain transient SPICE simulations . My analysis needs to cover the entire frequency range-from static DC up to several gigahertz. When I run standard AC S-parameter extractions in Hybrid Solvers, the solver extrapolates data at low frequencies ( below 100 kHz down to 0 Hz ). As a result, the low-frequency plane resistance ( R_dc ) isn't accurate, which distorts low-frequency die-bump impedance ( Z_die) plots and results in miscalculated bulk decoupling capacitor requirements. Additionally, if I run transient circuit simulations using these extrapolated models, my SPICE solver often experiences convergence issues due to non-physical DC offsets. How can I configure PowerSI to include an exact 0 Hz static DC point in my S-parameter extractions so I don't rely on mathematical extrapolation? Thankyou in advance.Sigrityhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/clarity-3d-solver/66307/exploring-3d-via-modeling-and-simulation-using-sigrity-x-and-clarity-3d-solverThu, 03 Sep 2026 16:43:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d83f0236-8c52-4634-a434-bc97eb666876ShivaShankarMAs data rates continue to increase, vias become a critical part of the signal path and can significantly influence overall channel performance. Accurate 3D via modeling helps engineers better understand the impact of via discontinuities, parasitic effects, return paths, and routing constraints on signal integrity. Cadence Sigrity Topology Workbench includes the Aurora Via Wizard , which enables users to create detailed 3D via structures, visualize the geometry, extract EM-accurate models using the Clarity 3D field solver, and use those models directly in system-level simulations. Key capabilities include: Defining custom stackups and cross-sections Creating single-ended or differential via structures Configuring padstacks, return paths, and keepout regions Visualizing 3D via geometry Extracting S-Parameter models using Clarity 3D Integrating the extracted via models into Topology Workbench simulations Analyzing waveform behavior and channel performance The workflow begins by adding a Via block in Topology Workbench and launching the Aurora Via Wizard from the Via Properties panel. A typical flow includes: 1. Define the Cross-Section. Create the stackup and plane definitions required for accurate via modeling. Proper reference planes are essential for successful port definition and EM extraction. 2. Configure Padstacks and Via Structures. Select padstacks, create single-ended or differential via structures, and define return vias, spacing, angles, and keepout regions. 3. Visualize the 3D Geometry. Review the generated via structure in a 3D environment to verify the physical implementation before extraction. 4. Extract the Via Model. Generate an EM-accurate S-Parameter model using the Clarity 3D field solver and automatically assign the model to the Via block in Topology Workbench. 5. Simulate and Analyze. Connect the extracted via model to transmitter and receiver blocks, perform transient simulations, and evaluate waveform quality and signal integrity metrics. By incorporating realistic via behavior into early design analysis, engineers can improve correlation between simulation and hardware performance while gaining deeper insight into channel discontinuities and interconnect effects. To learn more about 3D via modeling and simulation workflows, explore the Aurora Via Wizard capabilities available in Sigrity Topology Workbench. Click here for more details on 3D via modeling and simulation using Sigrity. Have you used 3D via models in your high-speed designs? What challenges or best practices have you observed when modeling vias for SI analysis? Share your thoughts in the comments below. Thanks & Regards, Shiva Shankar Mclarity3dsolverSignal IntegrityviaSigritysimulationhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/clarity-3d-solver/66297/join-us-on-wednesday-sep-16th-2026-for-our-next-live-ask-me-anything-session-on-trusting-simulation-clarity-at-50-ghz-and-beyond-and-discover-how-to-achieve-accurate-reliable-results-for-next-generation-high-speed-designsMon, 31 Aug 2026 06:06:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7cad7e82-8244-4829-887f-95a78ce87154Renu VibhaDon't miss our next learning session, designed to bridge cutting-edge theory with real-world implementation. Moderated by a Cadence engineer, the discussion will provide practical guidance, proven techniques, and opportunities to engage directly with experts. Wednesday, September 16, 2026 ⏰ 8:30 PM - 9:30 PM IST Topic: Trusting Simulation Clarity at 50 GHz and Beyond ✅ Ask your questions ✅ Learn from industry experts ✅ Explore proven techniques ✅ Gain practical takeaways you can apply right awayhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66265/automated-layout-validation-during-pcb-package-translation-in-sigrity-clarity/1409250Thu, 27 Aug 2026 08:14:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a1172227-eae1-49e4-9b89-e05b9586b8adAK20250609765Hi Cistheta, Yes. Sigrity and Clarity provide a Layout Validation feature that can automatically perform layout integrity checks during PCB or IC Package translation into the Sigrity/Clarity environment. When Layout Validation is enabled, the tool automatically runs a comprehensive set of error-checking functions during the translation process and can detect issues such as: Floating Nodes Geometry Errors Short Circuits Open Circuits In addition to detecting these issues, the tool can: Mark error locations directly on the layout Display warning messages for detected short circuits Control warning output limits Ignore specific warnings, such as short circuits between REF_plane and GND nets The feature can be enabled through: Tools → Options → Edit Options → Translator → Settings → Layout Validation Once enabled, validation is performed automatically during the translation of supported databases such as Cadence Allegro (.brd), ODB++, and Gerber designs into the Sigrity/Clarity environment. For automation workflows, the following TCL command can be used: sigrity::spdif_option LayoutValidation 1 1 = Enable Layout Validation 0 = Disable Layout Validation This option acts as a master validation switch , automatically executing the available layout integrity checks and applying the configured error-reporting behavior during translation. Best regards, Alokhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/clarity-3d-solver/66289/how-accurate-are-your-connector-s-parametersWed, 26 Aug 2026 06:02:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2f352037-cb80-43a2-a817-ab8028d45b71Renu VibhaEver wondered how precise your connector modeling is in complex PCB environments? Are you capturing all parasitic effects? Explore the possibilities here Clarity 3D Workbench S-parameter Extraction for Connector on PCBhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409202Wed, 19 Aug 2026 15:11:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b65d951c-cf16-4b48-aad1-bcc7f34375b7AK20250609765Thank you everyone for the great questions and engagement today. We will follow up on pending items shortly and appreciate your participation.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409201Wed, 19 Aug 2026 15:09:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0e9c3eb9-7a7c-46f9-869c-49c34baecb0cAK20250609765Thank you for the question. When a channel fails compliance testing, engineers typically investigate insertion loss, return loss, crosstalk, ISI, eye margin, and SNR . The goal is to determine whether the failure is caused by excessive channel attenuation, reflections from impedance discontinuities, coupling from aggressor nets, or degraded receiver margin. In practice, S21 (insertion loss), S11 (return loss), crosstalk, eye opening, and SNR are among the most important indicators used to isolate the root cause of a compliance failure.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409200Wed, 19 Aug 2026 15:04:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ee33efa8-428c-4fae-9f25-2d1af16a5106AK20250609765The handoff typically breaks down when the logical connectivity used during topology creation no longer matches the physical implementation. Pin-name mismatches, component-definition differences, or connectivity mapping issues can prevent correct constraint transfer, forcing manual re-assignment of routing constraints in the layout flow. Maintaining consistent schematic-to-layout mapping is key.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409199Wed, 19 Aug 2026 14:57:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d0ddd603-c619-4211-aab8-ecf7b4afffcdCF202606104231When a channel fails compliance testing , what SI metrics is typically investigated?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409198Wed, 19 Aug 2026 14:54:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0c947733-3416-433c-8979-a4361943e9d2EDAHutDuring pre layout engineer creates a tuned LPDDR4 memory topology with specific termination resistors using generic schematic nodes … when transferring this to physical layout , mismatching pin names between the schematic symbols and the actual layout footprints break the net connectivity mapping in Aurora .. this completely resets the constraint manager rules, forcing the layout team to manually reassign routing constraints from scratchhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409197Wed, 19 Aug 2026 14:54:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6295edff-319d-4be9-ba90-a3c95a56af03AK20250609765Thank you for the question. AI servers and high-performance computing (HPC) systems introduce several unique challenges for signal integrity (SI) engineers: Heterogeneous Architectures: The integration of various processing units, such as CPUs, GPUs, and AI processors, requires careful management of signal integrity across different components, which can complicate design and validation processes. High-Speed Signaling: The demand for high-speed data transfer increases the risk of signal integrity issues, including crosstalk, attenuation, and reflections. Engineers must implement advanced techniques to mitigate these effects. Memory Bandwidth Limitations: The "memory wall" phenomenon, where memory bandwidth does not scale with the number of cores, poses challenges in ensuring that data can be efficiently accessed and processed without bottlenecks. Thermal Management: Increased power consumption from high-performance components generates heat, which can affect signal integrity. Engineers must design effective cooling solutions to maintain optimal operating conditions. Electromagnetic Interference (EMI): The complexity of modern AI workloads can lead to increased EMI, necessitating careful design to minimize interference and ensure compliance with regulatory standards. Complex Routing Constraints: The intricate layouts required for high-speed signals on PCBs can lead to routing challenges, requiring innovative design strategies to maintain signal integrity. Modular Designs: The shift towards disaggregated architectures and modular designs, facilitated by standards like UCIe, requires SI engineers to adapt to new connectivity standards and ensure compatibility across diverse components. Addressing these challenges is crucial for the successful deployment of AI servers and HPC systems, ensuring reliable performance and efficiency in demanding environments.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409196Wed, 19 Aug 2026 14:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:892361ba-5118-4e08-aaa2-d4fc91ffd8ecAK20250609765Thank you for the question. Before running detailed SI simulations, I would recommend using the PowerSI ERC - Trace Imp/Cpl/Ref Check workflow. While impedance may be within specification, SI issues can still arise from excessive coupling, missing or discontinuous reference planes, and localized routing violations . The ERC workflow automatically checks these conditions and reports violations through detailed tables and layout overlays, making it easy to identify the exact trace segments responsible for potential SI degradation. This allows layout issues to be corrected early, reducing simulation iterations and improving overall design quality.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409195Wed, 19 Aug 2026 14:45:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:71b09034-6a20-44ab-a1ee-7f62d2e8b257cistheta07In a high-speed DDR or SerDes design, impedance may be within specification, yet signal integrity issues can still occur. What layout-related factors should be investigated to identify the root cause before running detailed simulations?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409194Wed, 19 Aug 2026 14:44:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f58cc4e8-2371-41c9-8209-de9b1e514402EDAHutWhere does the handoff from schematic driven topologies to physical layout in Cadence Sigrity Aurora break down the most ?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409193Wed, 19 Aug 2026 14:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e77df1cc-32bc-4b94-be6a-0aa11c70b22aCF202606104231What new challenged does AI servers and high performance computing systems present for SI Engineers. Can you throw some lighthttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409192Wed, 19 Aug 2026 14:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e837711d-9668-411c-80c0-3d66b81726cdEDAHutHelpful thankshttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409191Wed, 19 Aug 2026 14:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a0b36045-eeb7-4f4b-af0e-561631f0671dAK20250609765Thank you for the question. A typical example is a high-speed PCIe or SerDes channel where the eye diagram fails to meet the required margin. By analyzing S21 (insertion loss) , engineers can identify excessive channel attenuation at higher frequencies. The root cause is often excessive trace length, via discontinuities, connectors, or a high-loss dielectric material. After optimizing the channel geometry or selecting a lower-loss stackup, the insertion loss improves, leading to better signal quality and improved eye opening. Therefore, S21 is commonly used to verify that the channel meets its loss budget and can support the target data rate before manufacturing.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409190Wed, 19 Aug 2026 14:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:33882359-0af3-4390-abb6-0380b6e31dcdAK20250609765Thank you for the question. To maintain the validity of pre-layout signal integrity (SI) results when the PCB stackup changes during the design cycle, follow these steps: Correctly Model Devices: Ensure that all devices are accurately modeled. This is crucial for the validity of pre-layout simulations. Reassess Design Constraints: After any changes to the stackup, reassess the design constraints that were initially applied. This helps in identifying any new requirements or adjustments needed. Utilize Model Assignment Utility: Use the Model Assignment utility to associate device models with schematic components. This ensures that the updated stackup is reflected in the simulations. Iterative Analysis: Conduct iterative analyses after stackup modifications. This allows for adjustments based on the new stackup configuration and ensures that the results remain relevant. Documentation and Archiving: Keep detailed records of all changes and their impacts on SI results. This aids in tracking the evolution of the design and understanding the implications of stackup changes. By following these practices, you can ensure that your pre-layout SI results remain valid and reliable throughout the design process