https://community.cadence.com/cadence_technology_forums/system-analysis/en-USTelligent Community 13https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409202Wed, 19 Aug 2026 15:11:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b65d951c-cf16-4b48-aad1-bcc7f34375b7AK20250609765Thank you everyone for the great questions and engagement today. We will follow up on pending items shortly and appreciate your participation.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409201Wed, 19 Aug 2026 15:09:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0e9c3eb9-7a7c-46f9-869c-49c34baecb0cAK20250609765Thank you for the question. When a channel fails compliance testing, engineers typically investigate insertion loss, return loss, crosstalk, ISI, eye margin, and SNR . The goal is to determine whether the failure is caused by excessive channel attenuation, reflections from impedance discontinuities, coupling from aggressor nets, or degraded receiver margin. In practice, S21 (insertion loss), S11 (return loss), crosstalk, eye opening, and SNR are among the most important indicators used to isolate the root cause of a compliance failure.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409200Wed, 19 Aug 2026 15:04:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ee33efa8-428c-4fae-9f25-2d1af16a5106AK20250609765The handoff typically breaks down when the logical connectivity used during topology creation no longer matches the physical implementation. Pin-name mismatches, component-definition differences, or connectivity mapping issues can prevent correct constraint transfer, forcing manual re-assignment of routing constraints in the layout flow. Maintaining consistent schematic-to-layout mapping is key.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409199Wed, 19 Aug 2026 14:57:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d0ddd603-c619-4211-aab8-ecf7b4afffcdCF202606104231When a channel fails compliance testing , what SI metrics is typically investigated?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409198Wed, 19 Aug 2026 14:54:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0c947733-3416-433c-8979-a4361943e9d2EDAHutDuring pre layout engineer creates a tuned LPDDR4 memory topology with specific termination resistors using generic schematic nodes … when transferring this to physical layout , mismatching pin names between the schematic symbols and the actual layout footprints break the net connectivity mapping in Aurora .. this completely resets the constraint manager rules, forcing the layout team to manually reassign routing constraints from scratchhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409197Wed, 19 Aug 2026 14:54:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6295edff-319d-4be9-ba90-a3c95a56af03AK20250609765Thank you for the question. AI servers and high-performance computing (HPC) systems introduce several unique challenges for signal integrity (SI) engineers: Heterogeneous Architectures: The integration of various processing units, such as CPUs, GPUs, and AI processors, requires careful management of signal integrity across different components, which can complicate design and validation processes. High-Speed Signaling: The demand for high-speed data transfer increases the risk of signal integrity issues, including crosstalk, attenuation, and reflections. Engineers must implement advanced techniques to mitigate these effects. Memory Bandwidth Limitations: The "memory wall" phenomenon, where memory bandwidth does not scale with the number of cores, poses challenges in ensuring that data can be efficiently accessed and processed without bottlenecks. Thermal Management: Increased power consumption from high-performance components generates heat, which can affect signal integrity. Engineers must design effective cooling solutions to maintain optimal operating conditions. Electromagnetic Interference (EMI): The complexity of modern AI workloads can lead to increased EMI, necessitating careful design to minimize interference and ensure compliance with regulatory standards. Complex Routing Constraints: The intricate layouts required for high-speed signals on PCBs can lead to routing challenges, requiring innovative design strategies to maintain signal integrity. Modular Designs: The shift towards disaggregated architectures and modular designs, facilitated by standards like UCIe, requires SI engineers to adapt to new connectivity standards and ensure compatibility across diverse components. Addressing these challenges is crucial for the successful deployment of AI servers and HPC systems, ensuring reliable performance and efficiency in demanding environments.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409196Wed, 19 Aug 2026 14:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:892361ba-5118-4e08-aaa2-d4fc91ffd8ecAK20250609765Thank you for the question. Before running detailed SI simulations, I would recommend using the PowerSI ERC - Trace Imp/Cpl/Ref Check workflow. While impedance may be within specification, SI issues can still arise from excessive coupling, missing or discontinuous reference planes, and localized routing violations . The ERC workflow automatically checks these conditions and reports violations through detailed tables and layout overlays, making it easy to identify the exact trace segments responsible for potential SI degradation. This allows layout issues to be corrected early, reducing simulation iterations and improving overall design quality.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409195Wed, 19 Aug 2026 14:45:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:71b09034-6a20-44ab-a1ee-7f62d2e8b257cistheta07In a high-speed DDR or SerDes design, impedance may be within specification, yet signal integrity issues can still occur. What layout-related factors should be investigated to identify the root cause before running detailed simulations?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409194Wed, 19 Aug 2026 14:44:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f58cc4e8-2371-41c9-8209-de9b1e514402EDAHutWhere does the handoff from schematic driven topologies to physical layout in Cadence Sigrity Aurora break down the most ?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409193Wed, 19 Aug 2026 14:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e77df1cc-32bc-4b94-be6a-0aa11c70b22aCF202606104231What new challenged does AI servers and high performance computing systems present for SI Engineers. Can you throw some lighthttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409192Wed, 19 Aug 2026 14:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e837711d-9668-411c-80c0-3d66b81726cdEDAHutHelpful thankshttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409191Wed, 19 Aug 2026 14:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a0b36045-eeb7-4f4b-af0e-561631f0671dAK20250609765Thank you for the question. A typical example is a high-speed PCIe or SerDes channel where the eye diagram fails to meet the required margin. By analyzing S21 (insertion loss) , engineers can identify excessive channel attenuation at higher frequencies. The root cause is often excessive trace length, via discontinuities, connectors, or a high-loss dielectric material. After optimizing the channel geometry or selecting a lower-loss stackup, the insertion loss improves, leading to better signal quality and improved eye opening. Therefore, S21 is commonly used to verify that the channel meets its loss budget and can support the target data rate before manufacturing.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409190Wed, 19 Aug 2026 14:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:33882359-0af3-4390-abb6-0380b6e31dcdAK20250609765Thank you for the question. To maintain the validity of pre-layout signal integrity (SI) results when the PCB stackup changes during the design cycle, follow these steps: Correctly Model Devices: Ensure that all devices are accurately modeled. This is crucial for the validity of pre-layout simulations. Reassess Design Constraints: After any changes to the stackup, reassess the design constraints that were initially applied. This helps in identifying any new requirements or adjustments needed. Utilize Model Assignment Utility: Use the Model Assignment utility to associate device models with schematic components. This ensures that the updated stackup is reflected in the simulations. Iterative Analysis: Conduct iterative analyses after stackup modifications. This allows for adjustments based on the new stackup configuration and ensures that the results remain relevant. Documentation and Archiving: Keep detailed records of all changes and their impacts on SI results. This aids in tracking the evolution of the design and understanding the implications of stackup changes. By following these practices, you can ensure that your pre-layout SI results remain valid and reliable throughout the design processhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409189Wed, 19 Aug 2026 14:21:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a7bcc9b0-c3c5-411d-97c2-4cd7ca70418eCF202606104231Can you share example where analysing insertion loss (s21) helped identify and resolve a signal integrity in a high speed design?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409188Wed, 19 Aug 2026 14:18:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d5659e64-f551-4d45-bf1f-702e23eaf081EDAHutThank you for hosting. One question… how to prevent per layout model from giving a false sense of security when stack up definitions change mid stream ?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409187Wed, 19 Aug 2026 14:15:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:08ab1ccf-26e9-4ed3-ac12-586d032c1a23AK20250609765Thank you for the question. In real-world PCB and package design, S-parameters are used to characterize how signals propagate through interconnects , while return loss (S11) is used to measure how much signal energy is reflected back due to impedance discontinuities. For example, in a DDR5 channel, engineers can extract S-parameters for the traces, vias, connectors, and package and evaluate return loss across the operating frequency range. If excessive reflections are identified, the routing or via structure can be optimized before fabrication. This helps reduce SI issues during hardware bring-up and increases the likelihood of a successful first prototype spin.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409186Wed, 19 Aug 2026 14:08:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:4e22ed68-dbaa-476d-baac-f7323dc3c589AK20250609765To get us started, one common question we often hear is: How can we identify potential SI/PI issues early in the design cycle, before the board goes to fabrication? Here’s a quick perspective: Cadence Sigrity Aurora is a signal and power integrity (SI/PI) analysis solution tightly integrated into the Allegro PCB design environment. Its In-Design Analysis (IDA) capabilities enable engineers to perform analysis directly within the PCB environment and visualize the impact of design changes in real time. Aurora also provides layout analysis workflows for evaluating key concerns such as impedance, coupling, crosstalk, return paths, reflections, and IR drop. In addition, Sigrity Topology Explorer enables early what-if analysis to evaluate different design scenarios before committing to the final PCB implementation. By identifying potential SI/PI-related layout issues early, engineers can make informed design decisions and help avoid potentially expensive board respins. Has anyone encountered a similar challenge in their designs?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409185Wed, 19 Aug 2026 14:08:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:918ff4be-1baa-4d85-8687-9e8460a6a7ecCF202606104231In practical PCB or package designs , how are S-parameters and return loss measurements used ? Give me a real world example to validate performance before a product goes into manufacturing?https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409184Wed, 19 Aug 2026 14:04:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9df7bf50-40a2-4a51-a955-87ad3d0a1855AK20250609765Welcome everyone and thank you for joining today’s Expert Session. Please feel free to post your questions any time—we’re here to helphttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66233/si-engineers-this-one-s-for-you---live-experts-session-on-aug-19th-2026/1409177Tue, 18 Aug 2026 07:45:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:5ca141c4-d0ff-4236-a0ab-cec6cdd17cc3Renu VibhaDon't miss this session on August 19th, 7:30 PM to 8:30 PM IST . We look forward to welcoming you and seeing you there!