############################################################### # Generated by: Cadence Innovus 15.23-s045_1 # OS: Linux x86_64(Host ID ams51) # Generated on: Mon Apr 17 21:44:11 2023 # Design: CDR_INTEGRATEDv2 # Command: timeDesign -signoff -hold ############################################################### Path 1: VIOLATED Hold Check with Pin DLFOP1_CDR_Kp_LS7_reg[2]/CP Endpoint: DLFOP1_CDR_Kp_LS7_reg[2]/D (v) checked with leading edge of 'clk' Beginpoint: Kpctrl[1] (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.045 + Hold 0.021 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.166 Arrival Time -0.116 Slack Time -0.283 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +--------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------+------+-----------+---------+-------+---------+----------| | Kpctrl[1] | ^ | Kpctrl[1] | | | -0.126 | 0.156 | | g805/B2 | ^ | Kpctrl[1] | INR3D0 | 0.000 | -0.126 | 0.156 | | g805/ZN | v | n_202 | INR3D0 | 0.010 | -0.116 | 0.166 | | DLFOP1_CDR_Kp_LS7_reg[2]/D | v | n_202 | DFCNQD1 | 0.000 | -0.116 | 0.166 | +--------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +-----------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-----------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.283 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.282 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.238 | | DLFOP1_CDR_Kp_LS7_reg[2]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.045 | -0.238 | +-----------------------------------------------------------------------------------+ Path 2: VIOLATED Hold Check with Pin DLFOP1_CDR_Kp_LS7_reg[4]/CP Endpoint: DLFOP1_CDR_Kp_LS7_reg[4]/D (v) checked with leading edge of 'clk' Beginpoint: Kpctrl[0] (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.045 + Hold 0.021 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.166 Arrival Time -0.115 Slack Time -0.281 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +--------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------+------+-----------+---------+-------+---------+----------| | Kpctrl[0] | ^ | Kpctrl[0] | | | -0.126 | 0.154 | | g808/B1 | ^ | Kpctrl[0] | INR3D0 | 0.000 | -0.126 | 0.154 | | g808/ZN | v | n_199 | INR3D0 | 0.012 | -0.115 | 0.166 | | DLFOP1_CDR_Kp_LS7_reg[4]/D | v | n_199 | DFCNQD1 | 0.000 | -0.115 | 0.166 | +--------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +-----------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-----------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.281 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.280 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.236 | | DLFOP1_CDR_Kp_LS7_reg[4]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.045 | -0.235 | +-----------------------------------------------------------------------------------+ Path 3: VIOLATED Hold Check with Pin DLFOP1_CDR_Kp_LS7_reg[3]/CP Endpoint: DLFOP1_CDR_Kp_LS7_reg[3]/D (v) checked with leading edge of 'clk' Beginpoint: Kpctrl[1] (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.045 + Hold 0.021 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.166 Arrival Time -0.115 Slack Time -0.281 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +--------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------+------+-----------+---------+-------+---------+----------| | Kpctrl[1] | ^ | Kpctrl[1] | | | -0.127 | 0.154 | | g807/B1 | ^ | Kpctrl[1] | INR3D0 | 0.000 | -0.127 | 0.154 | | g807/ZN | v | n_200 | INR3D0 | 0.012 | -0.115 | 0.166 | | DLFOP1_CDR_Kp_LS7_reg[3]/D | v | n_200 | DFCNQD1 | 0.000 | -0.115 | 0.166 | +--------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +-----------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-----------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.281 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.280 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.236 | | DLFOP1_CDR_Kp_LS7_reg[3]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.045 | -0.235 | +-----------------------------------------------------------------------------------+ Path 4: VIOLATED Hold Check with Pin DLFOP1_CDR_Kp_LS7_reg[5]/CP Endpoint: DLFOP1_CDR_Kp_LS7_reg[5]/D (^) checked with leading edge of 'clk' Beginpoint: Kpctrl[0] (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.045 + Hold 0.006 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.151 Arrival Time -0.092 Slack Time -0.243 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +--------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------+------+-----------+---------+-------+---------+----------| | Kpctrl[0] | ^ | Kpctrl[0] | | | -0.126 | 0.117 | | g806/A2 | ^ | Kpctrl[0] | AN3D1 | 0.000 | -0.126 | 0.117 | | g806/Z | ^ | n_201 | AN3D1 | 0.035 | -0.092 | 0.151 | | DLFOP1_CDR_Kp_LS7_reg[5]/D | ^ | n_201 | DFCNQD1 | 0.000 | -0.092 | 0.151 | +--------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +-----------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-----------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.243 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.243 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.199 | | DLFOP1_CDR_Kp_LS7_reg[5]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.045 | -0.198 | +-----------------------------------------------------------------------------------+ Path 5: VIOLATED Hold Check with Pin DLFOP23_CDR_ADC_PICODE_reg[0]/CP Endpoint: DLFOP23_CDR_ADC_PICODE_reg[0]/D (v) checked with leading edge of 'clk' Beginpoint: ADCPI_OFFSET[0] (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.047 + Hold -0.005 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.142 Arrival Time -0.095 Slack Time -0.237 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +-----------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------------+------+-----------------+-------+-------+---------+----------| | ADCPI_OFFSET[0] | ^ | ADCPI_OFFSET[0] | | | -0.126 | 0.111 | | g2794/A | ^ | ADCPI_OFFSET[0] | HA1D0 | 0.001 | -0.126 | 0.112 | | g2794/S | v | n_55 | HA1D0 | 0.031 | -0.095 | 0.142 | | DLFOP23_CDR_ADC_PICODE_reg[0]/D | v | n_55 | EDFD1 | 0.000 | -0.095 | 0.142 | +-----------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.237 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.237 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.193 | | DLFOP23_CDR_ADC_PICODE_reg[0]/CP | ^ | CTS_6 | EDFD1 | 0.003 | 0.047 | -0.190 | +---------------------------------------------------------------------------------------+ Path 6: VIOLATED Hold Check with Pin DLFOP23_CDR_ADC_PICODE_reg[1]/CP Endpoint: DLFOP23_CDR_ADC_PICODE_reg[1]/D (v) checked with leading edge of 'clk' Beginpoint: ADCPI_OFFSET[1] (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.047 + Hold -0.006 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.141 Arrival Time -0.079 Slack Time -0.220 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +-----------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------------+------+-----------------+-------+-------+---------+----------| | ADCPI_OFFSET[1] | ^ | ADCPI_OFFSET[1] | | | -0.126 | 0.094 | | g2767/B | ^ | ADCPI_OFFSET[1] | FA1D0 | 0.001 | -0.126 | 0.095 | | g2767/S | v | n_81 | FA1D0 | 0.047 | -0.079 | 0.141 | | DLFOP23_CDR_ADC_PICODE_reg[1]/D | v | n_81 | EDFD1 | 0.000 | -0.079 | 0.141 | +-----------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.220 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.220 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.176 | | DLFOP23_CDR_ADC_PICODE_reg[1]/CP | ^ | CTS_6 | EDFD1 | 0.003 | 0.047 | -0.173 | +---------------------------------------------------------------------------------------+ Path 7: VIOLATED Hold Check with Pin DLFOP23_CDR_Kp_plus_Ki_reg[10]/CP Endpoint: DLFOP23_CDR_Kp_plus_Ki_reg[10]/D (^) checked with leading edge of 'clk' Beginpoint: Kictrl[1] (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.047 + Hold 0.006 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.153 Arrival Time -0.052 Slack Time -0.206 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +---------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------------+------+-----------+----------+-------+---------+----------| | Kictrl[1] | ^ | Kictrl[1] | | | -0.126 | 0.079 | | g2829/A1 | ^ | Kictrl[1] | CKND2D2 | 0.000 | -0.126 | 0.079 | | g2829/ZN | v | n_26 | CKND2D2 | 0.021 | -0.106 | 0.100 | | g2659/A2 | v | n_26 | MOAI22D1 | 0.000 | -0.106 | 0.100 | | g2659/ZN | ^ | n_165 | MOAI22D1 | 0.023 | -0.083 | 0.123 | | g2657/C | ^ | n_165 | AO221D0 | 0.000 | -0.083 | 0.123 | | g2657/Z | ^ | n_166 | AO221D0 | 0.031 | -0.052 | 0.153 | | DLFOP23_CDR_Kp_plus_Ki_reg[10]/D | ^ | n_166 | DFCND1 | 0.000 | -0.052 | 0.153 | +---------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-----------------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.206 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.205 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.161 | | DLFOP23_CDR_Kp_plus_Ki_reg[10]/CP | ^ | CTS_6 | DFCND1 | 0.003 | 0.047 | -0.158 | +----------------------------------------------------------------------------------------+ Path 8: VIOLATED Hold Check with Pin DLFOP23_CDR_Kpi_ctrl_reg[1]/CP Endpoint: DLFOP23_CDR_Kpi_ctrl_reg[1]/D (v) checked with leading edge of 'clk' Beginpoint: reset (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.047 + Hold 0.015 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.162 Arrival Time -0.041 Slack Time -0.203 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +-----------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-------------------------------+------+----------------+----------+-------+---------+----------| | reset | ^ | reset | | | -0.126 | 0.077 | | g2789/A2 | ^ | reset | MOAI22D1 | 0.003 | -0.123 | 0.080 | | g2789/ZN | v | n_62 | MOAI22D1 | 0.013 | -0.110 | 0.094 | | FE_PHC181_n_62/I | v | n_62 | DEL01 | 0.000 | -0.110 | 0.094 | | FE_PHC181_n_62/Z | v | FE_PHN181_n_62 | DEL01 | 0.069 | -0.041 | 0.162 | | DLFOP23_CDR_Kpi_ctrl_reg[1]/D | v | FE_PHN181_n_62 | DFD1 | 0.000 | -0.041 | 0.162 | +-----------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +-------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |--------------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.203 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.203 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.159 | | DLFOP23_CDR_Kpi_ctrl_reg[1]/CP | ^ | CTS_6 | DFD1 | 0.003 | 0.047 | -0.156 | +-------------------------------------------------------------------------------------+ Path 9: VIOLATED Hold Check with Pin DLFOP23_CDR_Kp_plus_Ki_reg[9]/CP Endpoint: DLFOP23_CDR_Kp_plus_Ki_reg[9]/D (^) checked with leading edge of 'clk' Beginpoint: Kictrl[1] (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.047 + Hold 0.008 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.155 Arrival Time -0.037 Slack Time -0.192 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +--------------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------------+------+-----------------+----------+-------+---------+----------| | Kictrl[1] | ^ | Kictrl[1] | | | -0.126 | 0.065 | | g2829/A1 | ^ | Kictrl[1] | CKND2D2 | 0.000 | -0.126 | 0.065 | | g2829/ZN | v | n_26 | CKND2D2 | 0.021 | -0.106 | 0.086 | | g2661/A2 | v | n_26 | MOAI22D1 | 0.000 | -0.106 | 0.086 | | g2661/ZN | ^ | n_163 | MOAI22D1 | 0.023 | -0.083 | 0.109 | | g2660/C | ^ | n_163 | AO221D0 | 0.000 | -0.083 | 0.109 | | g2660/Z | ^ | n_164 | AO221D0 | 0.028 | -0.055 | 0.137 | | FE_PHC120_n_164/I | ^ | n_164 | CKBD1 | 0.000 | -0.055 | 0.137 | | FE_PHC120_n_164/Z | ^ | FE_PHN120_n_164 | CKBD1 | 0.017 | -0.037 | 0.155 | | DLFOP23_CDR_Kp_plus_Ki_reg[9]/D | ^ | FE_PHN120_n_164 | DFCND1 | 0.000 | -0.037 | 0.155 | +--------------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.192 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.191 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.147 | | DLFOP23_CDR_Kp_plus_Ki_reg[9]/CP | ^ | CTS_6 | DFCND1 | 0.002 | 0.047 | -0.145 | +---------------------------------------------------------------------------------------+ Path 10: VIOLATED Removal Check with Pin DLFOP23_CDR_Kp_plus_Ki_reg[5]/CP Endpoint: DLFOP23_CDR_Kp_plus_Ki_reg[5]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.030 Slack Time -0.181 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +-------------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-----------------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.140 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.142 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.157 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.157 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.211 | | DLFOP23_CDR_Kp_plus_Ki_reg[5]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.000 | 0.030 | 0.211 | +-------------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.181 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.181 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.137 | | DLFOP23_CDR_Kp_plus_Ki_reg[5]/CP | ^ | CTS_6 | DFCNQD1 | 0.002 | 0.046 | -0.135 | +----------------------------------------------------------------------------------------+ Path 11: VIOLATED Removal Check with Pin DLFOP23_CDR_Kp_plus_Ki_reg[4]/CP Endpoint: DLFOP23_CDR_Kp_plus_Ki_reg[4]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.030 Slack Time -0.181 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +-------------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-----------------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.140 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.142 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.157 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.157 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.211 | | DLFOP23_CDR_Kp_plus_Ki_reg[4]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.000 | 0.030 | 0.211 | +-------------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.181 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.137 | | DLFOP23_CDR_Kp_plus_Ki_reg[4]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.046 | -0.135 | +----------------------------------------------------------------------------------------+ Path 12: VIOLATED Removal Check with Pin DLFOP23_CDR_Kp_plus_Ki_reg[3]/CP Endpoint: DLFOP23_CDR_Kp_plus_Ki_reg[3]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.030 Slack Time -0.181 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +-------------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-----------------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.140 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.142 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.157 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.157 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.211 | | DLFOP23_CDR_Kp_plus_Ki_reg[3]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.000 | 0.030 | 0.211 | +-------------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.181 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.136 | | DLFOP23_CDR_Kp_plus_Ki_reg[3]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.046 | -0.135 | +----------------------------------------------------------------------------------------+ Path 13: VIOLATED Removal Check with Pin DLFOP1_CDR_Ki_reg[0]/CP Endpoint: DLFOP1_CDR_Ki_reg[0]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.045 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.030 Slack Time -0.181 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +---------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |--------------------------+------+---------------+--------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.140 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.157 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.157 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.211 | | DLFOP1_CDR_Ki_reg[0]/CDN | ^ | FE_OFN32_n_20 | DFCND1 | 0.000 | 0.030 | 0.211 | +---------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +--------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.181 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.136 | | DLFOP1_CDR_Ki_reg[0]/CP | ^ | CTS_6 | DFCND1 | 0.001 | 0.045 | -0.135 | +--------------------------------------------------------------------------------+ Path 14: VIOLATED Removal Check with Pin DLFOP1_CDR_Kp_LS7_reg[3]/CP Endpoint: DLFOP1_CDR_Kp_LS7_reg[3]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.045 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.030 Slack Time -0.181 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +--------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |------------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.140 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.157 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.157 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP1_CDR_Kp_LS7_reg[3]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.000 | 0.030 | 0.211 | +--------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +-----------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-----------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.181 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.136 | | DLFOP1_CDR_Kp_LS7_reg[3]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.045 | -0.135 | +-----------------------------------------------------------------------------------+ Path 15: VIOLATED Removal Check with Pin DLFOP23_CDR_Kp_plus_Ki_reg[2]/CP Endpoint: DLFOP23_CDR_Kp_plus_Ki_reg[2]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.045 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.030 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +-------------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-----------------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.140 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.157 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.157 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP23_CDR_Kp_plus_Ki_reg[2]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.000 | 0.030 | 0.211 | +-------------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.136 | | DLFOP23_CDR_Kp_plus_Ki_reg[2]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.045 | -0.135 | +----------------------------------------------------------------------------------------+ Path 16: VIOLATED Removal Check with Pin DLFOP1_CDR_Kp_LS7_reg[4]/CP Endpoint: DLFOP1_CDR_Kp_LS7_reg[4]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.045 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.030 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +--------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |------------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.140 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.157 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.157 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP1_CDR_Kp_LS7_reg[4]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.000 | 0.030 | 0.211 | +--------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +-----------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-----------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.136 | | DLFOP1_CDR_Kp_LS7_reg[4]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.045 | -0.135 | +-----------------------------------------------------------------------------------+ Path 17: VIOLATED Removal Check with Pin DLFOP1_CDR_Ki_reg[1]/CP Endpoint: DLFOP1_CDR_Ki_reg[1]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.031 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |--------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.140 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.157 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.157 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP1_CDR_Ki_reg[1]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.001 | 0.031 | 0.211 | +----------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.136 | | DLFOP1_CDR_Ki_reg[1]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 18: VIOLATED Removal Check with Pin DLFOP1_CDR_Ki_reg[8]/CP Endpoint: DLFOP1_CDR_Ki_reg[8]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.031 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |--------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.140 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.157 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.157 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP1_CDR_Ki_reg[8]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.001 | 0.031 | 0.211 | +----------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.136 | | DLFOP1_CDR_Ki_reg[8]/CP | ^ | CTS_6 | DFCNQD1 | 0.002 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 19: VIOLATED Removal Check with Pin DLFOP1_CDR_Kp_LS7_reg[2]/CP Endpoint: DLFOP1_CDR_Kp_LS7_reg[2]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.045 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.030 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +--------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |------------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.140 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.157 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.157 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP1_CDR_Kp_LS7_reg[2]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.000 | 0.030 | 0.211 | +--------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +-----------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-----------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.136 | | DLFOP1_CDR_Kp_LS7_reg[2]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.045 | -0.135 | +-----------------------------------------------------------------------------------+ Path 20: VIOLATED Removal Check with Pin DLFOP1_CDR_Kp_LS7_reg[5]/CP Endpoint: DLFOP1_CDR_Kp_LS7_reg[5]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.045 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.030 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +--------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |------------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.140 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.157 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.157 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP1_CDR_Kp_LS7_reg[5]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.000 | 0.030 | 0.211 | +--------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +-----------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-----------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.136 | | DLFOP1_CDR_Kp_LS7_reg[5]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.045 | -0.135 | +-----------------------------------------------------------------------------------+ Path 21: VIOLATED Removal Check with Pin DLFOP1_CDR_Ki_reg[2]/CP Endpoint: DLFOP1_CDR_Ki_reg[2]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.031 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |--------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP1_CDR_Ki_reg[2]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.001 | 0.031 | 0.211 | +----------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.136 | | DLFOP1_CDR_Ki_reg[2]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 22: VIOLATED Removal Check with Pin DLFOP23_CDR_Kp_plus_Ki_reg[1]/CP Endpoint: DLFOP23_CDR_Kp_plus_Ki_reg[1]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.031 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +-------------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-----------------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP23_CDR_Kp_plus_Ki_reg[1]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.001 | 0.031 | 0.211 | +-------------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.136 | | DLFOP23_CDR_Kp_plus_Ki_reg[1]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.046 | -0.134 | +----------------------------------------------------------------------------------------+ Path 23: VIOLATED Removal Check with Pin DLFOP1_CDR_Ki_reg[9]/CP Endpoint: DLFOP1_CDR_Ki_reg[9]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.031 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |--------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP1_CDR_Ki_reg[9]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.002 | 0.031 | 0.211 | +----------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.136 | | DLFOP1_CDR_Ki_reg[9]/CP | ^ | CTS_6 | DFCNQD1 | 0.002 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 24: VIOLATED Removal Check with Pin DLFOP1_CDR_Ki_reg[13]/CP Endpoint: DLFOP1_CDR_Ki_reg[13]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.212 Arrival Time 0.032 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +-----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP1_CDR_Ki_reg[13]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.002 | 0.032 | 0.212 | +-----------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.136 | | DLFOP1_CDR_Ki_reg[13]/CP | ^ | CTS_6 | DFCNQD1 | 0.002 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 25: VIOLATED Removal Check with Pin DLFOP1_CDR_Ki_reg[7]/CP Endpoint: DLFOP1_CDR_Ki_reg[7]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.212 Arrival Time 0.032 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |--------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP1_CDR_Ki_reg[7]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.002 | 0.032 | 0.212 | +----------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.135 | | DLFOP1_CDR_Ki_reg[7]/CP | ^ | CTS_6 | DFCNQD1 | 0.002 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 26: VIOLATED Removal Check with Pin DLFOP1_CDR_Ki_reg[6]/CP Endpoint: DLFOP1_CDR_Ki_reg[6]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.212 Arrival Time 0.032 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |--------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP1_CDR_Ki_reg[6]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.002 | 0.032 | 0.212 | +----------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.135 | | DLFOP1_CDR_Ki_reg[6]/CP | ^ | CTS_6 | DFCNQD1 | 0.002 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 27: VIOLATED Removal Check with Pin DLFOP1_CDR_Ki_reg[10]/CP Endpoint: DLFOP1_CDR_Ki_reg[10]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.212 Arrival Time 0.032 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +-----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP1_CDR_Ki_reg[10]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.002 | 0.032 | 0.212 | +-----------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.135 | | DLFOP1_CDR_Ki_reg[10]/CP | ^ | CTS_6 | DFCNQD1 | 0.002 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 28: VIOLATED Removal Check with Pin DLFOP1_CDR_Out_reg[0]/CP Endpoint: DLFOP1_CDR_Out_reg[0]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.031 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+---------------+--------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP1_CDR_Out_reg[0]/CDN | ^ | FE_OFN32_n_20 | DFCND1 | 0.002 | 0.031 | 0.211 | +----------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +--------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.135 | | DLFOP1_CDR_Out_reg[0]/CP | ^ | CTS_6 | DFCND1 | 0.001 | 0.046 | -0.134 | +--------------------------------------------------------------------------------+ Path 29: VIOLATED Removal Check with Pin DLFOP1_CDR_Ki_reg[3]/CP Endpoint: DLFOP1_CDR_Ki_reg[3]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.031 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |--------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.141 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP1_CDR_Ki_reg[3]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.002 | 0.031 | 0.211 | +----------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.135 | | DLFOP1_CDR_Ki_reg[3]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 30: VIOLATED Removal Check with Pin BBPD_CDR_dn_reg[0]/CP Endpoint: BBPD_CDR_dn_reg[0]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.212 Arrival Time 0.032 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +--------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.140 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | BBPD_CDR_dn_reg[0]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.002 | 0.032 | 0.212 | +--------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.135 | | BBPD_CDR_dn_reg[0]/CP | ^ | CTS_6 | DFCNQD1 | 0.002 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 31: VIOLATED Removal Check with Pin BBPD_CDR_up_reg[1]/CP Endpoint: BBPD_CDR_up_reg[1]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.212 Arrival Time 0.032 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +--------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.140 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | BBPD_CDR_up_reg[1]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.002 | 0.032 | 0.212 | +--------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.135 | | BBPD_CDR_up_reg[1]/CP | ^ | CTS_6 | DFCNQD1 | 0.002 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 32: VIOLATED Removal Check with Pin BBPD_CDR_up_reg[2]/CP Endpoint: BBPD_CDR_up_reg[2]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.212 Arrival Time 0.032 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +--------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.140 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | BBPD_CDR_up_reg[2]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.002 | 0.032 | 0.212 | +--------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.135 | | BBPD_CDR_up_reg[2]/CP | ^ | CTS_6 | DFCNQD1 | 0.002 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 33: VIOLATED Removal Check with Pin BBPD_CDR_dn_reg[4]/CP Endpoint: BBPD_CDR_dn_reg[4]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.032 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +--------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.140 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | BBPD_CDR_dn_reg[4]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.002 | 0.032 | 0.211 | +--------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.135 | | BBPD_CDR_dn_reg[4]/CP | ^ | CTS_6 | DFCNQD1 | 0.002 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 34: VIOLATED Removal Check with Pin DLFOP1_CDR_Ki_reg[5]/CP Endpoint: DLFOP1_CDR_Ki_reg[5]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.032 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |--------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.140 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP1_CDR_Ki_reg[5]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.002 | 0.032 | 0.211 | +----------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.135 | | DLFOP1_CDR_Ki_reg[5]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 35: VIOLATED Removal Check with Pin DLFOP1_CDR_Ki_reg[4]/CP Endpoint: DLFOP1_CDR_Ki_reg[4]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.032 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |--------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.140 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | DLFOP1_CDR_Ki_reg[4]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.002 | 0.032 | 0.211 | +----------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.135 | | DLFOP1_CDR_Ki_reg[4]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 36: VIOLATED Removal Check with Pin BBPD_CDR_dn_reg[1]/CP Endpoint: BBPD_CDR_dn_reg[1]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.032 Slack Time -0.180 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +-------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |------------------------+------+---------------+--------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.140 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.210 | | BBPD_CDR_dn_reg[1]/CDN | ^ | FE_OFN32_n_20 | DFCND1 | 0.002 | 0.032 | 0.211 | +-------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +--------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.180 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.135 | | BBPD_CDR_dn_reg[1]/CP | ^ | CTS_6 | DFCND1 | 0.002 | 0.046 | -0.134 | +--------------------------------------------------------------------------------+ Path 37: VIOLATED Removal Check with Pin BBPD_CDR_dn_reg[3]/CP Endpoint: BBPD_CDR_dn_reg[3]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.032 Slack Time -0.179 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +--------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.140 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.209 | | BBPD_CDR_dn_reg[3]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.002 | 0.032 | 0.211 | +--------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.135 | | BBPD_CDR_dn_reg[3]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 38: VIOLATED Removal Check with Pin BBPD_CDR_up_reg[4]/CP Endpoint: BBPD_CDR_up_reg[4]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.065 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.211 Arrival Time 0.032 Slack Time -0.179 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +--------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.139 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.140 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.156 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.156 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.209 | | BBPD_CDR_up_reg[4]/CDN | ^ | FE_OFN32_n_20 | DFCNQD1 | 0.002 | 0.032 | 0.211 | +--------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.179 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.135 | | BBPD_CDR_up_reg[4]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.046 | -0.134 | +---------------------------------------------------------------------------------+ Path 39: VIOLATED Removal Check with Pin BBPD_CDR_up_reg[0]/CP Endpoint: BBPD_CDR_up_reg[0]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.062 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.209 Arrival Time 0.032 Slack Time -0.177 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +-------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |------------------------+------+---------------+--------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.136 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.137 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.153 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.153 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.207 | | BBPD_CDR_up_reg[0]/CDN | ^ | FE_OFN32_n_20 | DFCND2 | 0.002 | 0.032 | 0.209 | +-------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +--------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.177 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.176 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.132 | | BBPD_CDR_up_reg[0]/CP | ^ | CTS_6 | DFCND2 | 0.002 | 0.046 | -0.131 | +--------------------------------------------------------------------------------+ Path 40: VIOLATED Removal Check with Pin BBPD_CDR_up_reg[3]/CP Endpoint: BBPD_CDR_up_reg[3]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.062 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.209 Arrival Time 0.032 Slack Time -0.177 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +-------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |------------------------+------+---------------+--------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.136 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.137 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.153 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.153 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.207 | | BBPD_CDR_up_reg[3]/CDN | ^ | FE_OFN32_n_20 | DFCND2 | 0.002 | 0.032 | 0.209 | +-------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +--------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.177 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.176 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.132 | | BBPD_CDR_up_reg[3]/CP | ^ | CTS_6 | DFCND2 | 0.002 | 0.046 | -0.131 | +--------------------------------------------------------------------------------+ Path 41: VIOLATED Removal Check with Pin BBPD_CDR_dn_reg[2]/CP Endpoint: BBPD_CDR_dn_reg[2]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.062 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.208 Arrival Time 0.032 Slack Time -0.177 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +-------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |------------------------+------+---------------+--------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.136 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.137 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.153 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.153 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.206 | | BBPD_CDR_dn_reg[2]/CDN | ^ | FE_OFN32_n_20 | DFCND2 | 0.002 | 0.032 | 0.208 | +-------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +--------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.177 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.176 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.132 | | BBPD_CDR_dn_reg[2]/CP | ^ | CTS_6 | DFCND2 | 0.002 | 0.046 | -0.131 | +--------------------------------------------------------------------------------+ Path 42: VIOLATED Removal Check with Pin DLFOP1_CDR_Ki_reg[11]/CP Endpoint: DLFOP1_CDR_Ki_reg[11]/CDN (^) checked with leading edge of 'clk' Beginpoint: reset (v) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Removal 0.059 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.205 Arrival Time 0.032 Slack Time -0.174 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.041 = Beginpoint Arrival Time -0.041 Timing Path: +-----------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+---------------+---------+-------+---------+----------| | reset | v | reset | | | -0.041 | 0.133 | | g2834/I | v | reset | CKND0 | 0.001 | -0.039 | 0.135 | | g2834/ZN | ^ | n_20 | CKND0 | 0.015 | -0.024 | 0.150 | | FE_OFC32_n_20/I | ^ | n_20 | BUFFD6 | 0.000 | -0.024 | 0.150 | | FE_OFC32_n_20/Z | ^ | FE_OFN32_n_20 | BUFFD6 | 0.054 | 0.030 | 0.204 | | DLFOP1_CDR_Ki_reg[11]/CDN | ^ | FE_OFN32_n_20 | DFCNQD4 | 0.002 | 0.032 | 0.205 | +-----------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.174 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.173 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.129 | | DLFOP1_CDR_Ki_reg[11]/CP | ^ | CTS_6 | DFCNQD4 | 0.002 | 0.046 | -0.128 | +---------------------------------------------------------------------------------+ Path 43: VIOLATED Hold Check with Pin DLFOP23_CDR_Kp_plus_Ki_reg[8]/CP Endpoint: DLFOP23_CDR_Kp_plus_Ki_reg[8]/D (^) checked with leading edge of 'clk' Beginpoint: Kictrl[1] (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.047 + Hold 0.006 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.154 Arrival Time -0.016 Slack Time -0.170 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +--------------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------------+------+-----------------+----------+-------+---------+----------| | Kictrl[1] | ^ | Kictrl[1] | | | -0.126 | 0.043 | | g2829/A1 | ^ | Kictrl[1] | CKND2D2 | 0.000 | -0.126 | 0.043 | | g2829/ZN | v | n_26 | CKND2D2 | 0.021 | -0.106 | 0.064 | | g2665/A2 | v | n_26 | MOAI22D1 | 0.000 | -0.106 | 0.064 | | g2665/ZN | ^ | n_160 | MOAI22D1 | 0.022 | -0.083 | 0.086 | | g2664/C | ^ | n_160 | AO221D0 | 0.000 | -0.083 | 0.086 | | g2664/Z | ^ | n_161 | AO221D0 | 0.032 | -0.051 | 0.118 | | FE_PHC119_n_161/I | ^ | n_161 | CKBD1 | 0.000 | -0.051 | 0.118 | | FE_PHC119_n_161/Z | ^ | FE_PHN119_n_161 | CKBD1 | 0.019 | -0.032 | 0.137 | | FE_PHC166_n_161/I | ^ | FE_PHN119_n_161 | CKBD1 | 0.000 | -0.032 | 0.137 | | FE_PHC166_n_161/Z | ^ | FE_PHN166_n_161 | CKBD1 | 0.016 | -0.016 | 0.154 | | DLFOP23_CDR_Kp_plus_Ki_reg[8]/D | ^ | FE_PHN166_n_161 | DFCND2 | 0.000 | -0.016 | 0.154 | +--------------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.170 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.169 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.125 | | DLFOP23_CDR_Kp_plus_Ki_reg[8]/CP | ^ | CTS_6 | DFCND2 | 0.003 | 0.047 | -0.123 | +---------------------------------------------------------------------------------------+ Path 44: VIOLATED Hold Check with Pin DLFOP23_CDR_Kpi_ctrl_reg[2]/CP Endpoint: DLFOP23_CDR_Kpi_ctrl_reg[2]/D (v) checked with leading edge of 'clk' Beginpoint: reset (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.047 + Hold 0.014 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.162 Arrival Time -0.007 Slack Time -0.169 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +-----------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-------------------------------+------+----------------+----------+-------+---------+----------| | reset | ^ | reset | | | -0.127 | 0.043 | | g2788/A2 | ^ | reset | MOAI22D1 | 0.003 | -0.123 | 0.046 | | g2788/ZN | v | n_63 | MOAI22D1 | 0.013 | -0.110 | 0.059 | | FE_PHC164_n_63/I | v | n_63 | DEL015 | 0.000 | -0.110 | 0.059 | | FE_PHC164_n_63/Z | v | FE_PHN164_n_63 | DEL015 | 0.103 | -0.007 | 0.162 | | DLFOP23_CDR_Kpi_ctrl_reg[2]/D | v | FE_PHN164_n_63 | DFD1 | 0.000 | -0.007 | 0.162 | +-----------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +-------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |--------------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.169 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.169 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.125 | | DLFOP23_CDR_Kpi_ctrl_reg[2]/CP | ^ | CTS_6 | DFD1 | 0.003 | 0.047 | -0.122 | +-------------------------------------------------------------------------------------+ Path 45: VIOLATED Hold Check with Pin DLFOP23_CDR_Kpi_ctrl_reg[0]/CP Endpoint: DLFOP23_CDR_Kpi_ctrl_reg[0]/D (v) checked with leading edge of 'clk' Beginpoint: reset (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.047 + Hold 0.014 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.162 Arrival Time -0.007 Slack Time -0.169 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +-----------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-------------------------------+------+----------------+----------+-------+---------+----------| | reset | ^ | reset | | | -0.127 | 0.042 | | g2790/A2 | ^ | reset | MOAI22D1 | 0.003 | -0.123 | 0.045 | | g2790/ZN | v | n_61 | MOAI22D1 | 0.013 | -0.110 | 0.058 | | FE_PHC163_n_61/I | v | n_61 | DEL015 | 0.000 | -0.110 | 0.058 | | FE_PHC163_n_61/Z | v | FE_PHN163_n_61 | DEL015 | 0.103 | -0.007 | 0.162 | | DLFOP23_CDR_Kpi_ctrl_reg[0]/D | v | FE_PHN163_n_61 | DFD1 | 0.000 | -0.007 | 0.162 | +-----------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +-------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |--------------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.169 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.168 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.124 | | DLFOP23_CDR_Kpi_ctrl_reg[0]/CP | ^ | CTS_6 | DFD1 | 0.003 | 0.047 | -0.121 | +-------------------------------------------------------------------------------------+ Path 46: VIOLATED Hold Check with Pin BBPD_CDR_dn_reg[1]/CP Endpoint: BBPD_CDR_dn_reg[1]/D (v) checked with leading edge of 'clk' Beginpoint: dataI[0] (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Hold 0.020 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.166 Arrival Time 0.010 Slack Time -0.156 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +-------------------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |-----------------------------+------+---------------------------+---------+-------+---------+----------| | dataI[0] | ^ | dataI[0] | | | -0.126 | 0.029 | | BBPD_CDR_g1140/A2 | ^ | dataI[0] | CKND2D4 | 0.000 | -0.126 | 0.029 | | BBPD_CDR_g1140/ZN | v | BBPD_CDR_n_2016 | CKND2D4 | 0.009 | -0.118 | 0.038 | | g3017/B | v | BBPD_CDR_n_2016 | OAI21D4 | 0.000 | -0.118 | 0.038 | | g3017/ZN | ^ | n_316 | OAI21D4 | 0.016 | -0.102 | 0.054 | | BBPD_CDR_g1101_dup/A2 | ^ | n_316 | NR2D3 | 0.000 | -0.102 | 0.054 | | BBPD_CDR_g1101_dup/ZN | v | FE_RN_15 | NR2D3 | 0.010 | -0.092 | 0.064 | | FE_RC_68_1/I | v | FE_RN_15 | CKND4 | 0.000 | -0.092 | 0.064 | | FE_RC_68_1/ZN | ^ | FE_OCPN63_BBPD_CDR_n_1966 | CKND4 | 0.014 | -0.078 | 0.078 | | FE_RC_14_0/A3 | ^ | FE_OCPN63_BBPD_CDR_n_1966 | XOR3D4 | 0.000 | -0.078 | 0.078 | | FE_RC_14_0/Z | ^ | BBPD_CDR_n_1883 | XOR3D4 | 0.031 | -0.047 | 0.109 | | FE_OCPC71_BBPD_CDR_n_1883/I | ^ | BBPD_CDR_n_1883 | BUFFD2 | 0.000 | -0.047 | 0.109 | | FE_OCPC71_BBPD_CDR_n_1883/Z | ^ | FE_OCPN71_BBPD_CDR_n_1883 | BUFFD2 | 0.020 | -0.027 | 0.129 | | FE_RC_1_1/A2 | ^ | FE_OCPN71_BBPD_CDR_n_1883 | OAI21D4 | 0.000 | -0.027 | 0.129 | | FE_RC_1_1/ZN | v | n_270 | OAI21D4 | 0.014 | -0.013 | 0.143 | | FE_RC_41_0/I | v | n_270 | CKND2 | 0.000 | -0.013 | 0.143 | | FE_RC_41_0/ZN | ^ | FE_RN_21_0 | CKND2 | 0.012 | -0.000 | 0.156 | | FE_RC_129_0/A2 | ^ | FE_RN_21_0 | AOI22D2 | 0.000 | -0.000 | 0.156 | | FE_RC_129_0/ZN | v | BBPD_CDR_n_1868 | AOI22D2 | 0.011 | 0.010 | 0.166 | | BBPD_CDR_dn_reg[1]/D | v | BBPD_CDR_n_1868 | DFCND1 | 0.000 | 0.010 | 0.166 | +-------------------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +--------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.156 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.155 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.111 | | BBPD_CDR_dn_reg[1]/CP | ^ | CTS_6 | DFCND1 | 0.002 | 0.046 | -0.110 | +--------------------------------------------------------------------------------+ Path 47: VIOLATED Hold Check with Pin BBPD_CDR_dn_reg[3]/CP Endpoint: BBPD_CDR_dn_reg[3]/D (v) checked with leading edge of 'clk' Beginpoint: dataI[0] (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.046 + Hold 0.021 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.167 Arrival Time 0.016 Slack Time -0.151 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +--------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------+------+-----------------+---------+-------+---------+----------| | dataI[0] | ^ | dataI[0] | | | -0.127 | 0.025 | | g3017/A2 | ^ | dataI[0] | OAI21D4 | 0.000 | -0.127 | 0.025 | | g3017/ZN | v | n_316 | OAI21D4 | 0.015 | -0.111 | 0.040 | | BBPD_CDR_g1101/A2 | v | n_316 | NR2D3 | 0.000 | -0.111 | 0.040 | | BBPD_CDR_g1101/ZN | ^ | BBPD_CDR_n_1966 | NR2D3 | 0.019 | -0.092 | 0.059 | | FE_RC_269_0/A1 | ^ | BBPD_CDR_n_1966 | OAI21D4 | 0.000 | -0.092 | 0.059 | | FE_RC_269_0/ZN | v | n_287 | OAI21D4 | 0.021 | -0.071 | 0.080 | | FE_RC_122_0/A2 | v | n_287 | ND2D4 | 0.000 | -0.071 | 0.080 | | FE_RC_122_0/ZN | ^ | BBPD_CDR_n_1914 | ND2D4 | 0.019 | -0.052 | 0.099 | | FE_RC_197_0/A1 | ^ | BBPD_CDR_n_1914 | OAI21D4 | 0.000 | -0.052 | 0.099 | | FE_RC_197_0/ZN | v | BBPD_CDR_n_1897 | OAI21D4 | 0.015 | -0.037 | 0.114 | | FE_RC_171_0/B1 | v | BBPD_CDR_n_1897 | IND2D4 | 0.000 | -0.037 | 0.114 | | FE_RC_171_0/ZN | ^ | FE_RN_113_0 | IND2D4 | 0.013 | -0.024 | 0.127 | | FE_RC_61_0/A1 | ^ | FE_RN_113_0 | AOI21D4 | 0.000 | -0.024 | 0.127 | | FE_RC_61_0/ZN | v | BBPD_CDR_n_1889 | AOI21D4 | 0.013 | -0.011 | 0.140 | | BBPD_CDR_g1007/B | v | BBPD_CDR_n_1889 | AOI21D4 | 0.000 | -0.011 | 0.140 | | BBPD_CDR_g1007/ZN | ^ | BBPD_CDR_n_1855 | AOI21D4 | 0.016 | 0.005 | 0.156 | | FE_RC_217_0/A1 | ^ | BBPD_CDR_n_1855 | OAI21D1 | 0.000 | 0.005 | 0.156 | | FE_RC_217_0/ZN | v | BBPD_CDR_n_1854 | OAI21D1 | 0.012 | 0.016 | 0.167 | | BBPD_CDR_dn_reg[3]/D | v | BBPD_CDR_n_1854 | DFCNQD1 | 0.000 | 0.016 | 0.167 | +--------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------+------+-------+---------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.151 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.150 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.045 | -0.107 | | BBPD_CDR_dn_reg[3]/CP | ^ | CTS_6 | DFCNQD1 | 0.001 | 0.046 | -0.105 | +---------------------------------------------------------------------------------+ Path 48: VIOLATED Hold Check with Pin DLFOP23_CDR_ADC_PICODE_reg[2]/CP Endpoint: DLFOP23_CDR_ADC_PICODE_reg[2]/E (v) checked with leading edge of 'clk' Beginpoint: reset (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.047 + Hold -0.007 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.140 Arrival Time -0.010 Slack Time -0.150 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +----------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------------+------+---------------+--------+-------+---------+----------| | reset | ^ | reset | | | -0.126 | 0.024 | | g2834/I | ^ | reset | CKND0 | 0.002 | -0.125 | 0.025 | | g2834/ZN | v | n_20 | CKND0 | 0.012 | -0.113 | 0.037 | | FE_OFC32_n_20/I | v | n_20 | BUFFD6 | 0.000 | -0.113 | 0.037 | | FE_OFC32_n_20/Z | v | FE_OFN32_n_20 | BUFFD6 | 0.045 | -0.068 | 0.083 | | FE_OFC38_n_20/I | v | FE_OFN32_n_20 | CKBD4 | 0.002 | -0.066 | 0.084 | | FE_OFC38_n_20/Z | v | FE_OFN38_n_20 | CKBD4 | 0.053 | -0.013 | 0.137 | | DLFOP23_CDR_ADC_PICODE_reg[2]/E | v | FE_OFN38_n_20 | EDFD1 | 0.003 | -0.010 | 0.140 | +----------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.150 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.150 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.106 | | DLFOP23_CDR_ADC_PICODE_reg[2]/CP | ^ | CTS_6 | EDFD1 | 0.003 | 0.047 | -0.103 | +---------------------------------------------------------------------------------------+ Path 49: VIOLATED Hold Check with Pin DLFOP23_CDR_ADC_PICODE_reg[1]/CP Endpoint: DLFOP23_CDR_ADC_PICODE_reg[1]/E (v) checked with leading edge of 'clk' Beginpoint: reset (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.047 + Hold -0.007 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.140 Arrival Time -0.010 Slack Time -0.150 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +----------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------------+------+---------------+--------+-------+---------+----------| | reset | ^ | reset | | | -0.126 | 0.024 | | g2834/I | ^ | reset | CKND0 | 0.002 | -0.125 | 0.025 | | g2834/ZN | v | n_20 | CKND0 | 0.012 | -0.113 | 0.037 | | FE_OFC32_n_20/I | v | n_20 | BUFFD6 | 0.000 | -0.113 | 0.037 | | FE_OFC32_n_20/Z | v | FE_OFN32_n_20 | BUFFD6 | 0.045 | -0.068 | 0.083 | | FE_OFC38_n_20/I | v | FE_OFN32_n_20 | CKBD4 | 0.002 | -0.066 | 0.084 | | FE_OFC38_n_20/Z | v | FE_OFN38_n_20 | CKBD4 | 0.053 | -0.013 | 0.137 | | DLFOP23_CDR_ADC_PICODE_reg[1]/E | v | FE_OFN38_n_20 | EDFD1 | 0.003 | -0.010 | 0.140 | +----------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.150 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.150 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.106 | | DLFOP23_CDR_ADC_PICODE_reg[1]/CP | ^ | CTS_6 | EDFD1 | 0.003 | 0.047 | -0.103 | +---------------------------------------------------------------------------------------+ Path 50: VIOLATED Hold Check with Pin DLFOP23_CDR_ADC_PICODE_reg[3]/CP Endpoint: DLFOP23_CDR_ADC_PICODE_reg[3]/E (v) checked with leading edge of 'clk' Beginpoint: reset (^) triggered by leading edge of '@' Path Groups: {default} Analysis View: analysis_ff Other End Arrival Time 0.047 + Hold -0.007 + Phase Shift 0.000 - CPPR Adjustment 0.000 + Uncertainty 0.100 = Required Time 0.140 Arrival Time -0.010 Slack Time -0.150 Clock Rise Edge 0.000 + Input Delay 0.000 + Drive Adjustment -0.126 = Beginpoint Arrival Time -0.126 Timing Path: +----------------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |---------------------------------+------+---------------+--------+-------+---------+----------| | reset | ^ | reset | | | -0.126 | 0.024 | | g2834/I | ^ | reset | CKND0 | 0.002 | -0.125 | 0.025 | | g2834/ZN | v | n_20 | CKND0 | 0.012 | -0.113 | 0.037 | | FE_OFC32_n_20/I | v | n_20 | BUFFD6 | 0.000 | -0.113 | 0.037 | | FE_OFC32_n_20/Z | v | FE_OFN32_n_20 | BUFFD6 | 0.045 | -0.068 | 0.082 | | FE_OFC38_n_20/I | v | FE_OFN32_n_20 | CKBD4 | 0.002 | -0.066 | 0.084 | | FE_OFC38_n_20/Z | v | FE_OFN38_n_20 | CKBD4 | 0.053 | -0.013 | 0.137 | | DLFOP23_CDR_ADC_PICODE_reg[3]/E | v | FE_OFN38_n_20 | EDFD1 | 0.003 | -0.010 | 0.140 | +----------------------------------------------------------------------------------------------+ Clock Rise Edge 0.000 = Beginpoint Arrival Time 0.000 Other End Path: +---------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------------+------+-------+--------+-------+---------+----------| | clk | ^ | clk | | | 0.000 | -0.150 | | CTS_ccl_BUF_clk_G0_L1_1/I | ^ | clk | CKBD16 | 0.001 | 0.001 | -0.150 | | CTS_ccl_BUF_clk_G0_L1_1/Z | ^ | CTS_6 | CKBD16 | 0.044 | 0.044 | -0.106 | | DLFOP23_CDR_ADC_PICODE_reg[3]/CP | ^ | CTS_6 | EDFD1 | 0.003 | 0.047 | -0.103 | +---------------------------------------------------------------------------------------+