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{\*\generator Msftedit 5.41.15.1507;}\viewkind4\uc1\pard\f0\fs20 ******* DISCLAIMER: This testcase is an example, provided ******\par
******* "as is" without express or implied warranty and with ******\par
******* no claim as to its suitability for any purpose. ******\par
******* This is for demonstration purpose only and may need ******\par
******* to be modified for use in a production environment. ******\par
******* README custom_border_sample ******\par
******* Date : Dec 2, 2008 ******\par
******* Version : 1.1 ******\par
******* Author: dholland ******\par
Tested with:Design Entry HDL SPB 16.01 s033 11/03/2008\par
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This sample library development project contains a buildlib with 3 sample connectors, version 1 (single pin) and version 2 (all elect pins) as well as a schematic and associated board containing two of each of the 3 connectors: \par
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1. conn_12 Plug, pins 1 thru 12, mtg holes pins 13 & 14\par
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2. conn_24 Receptacle, pins A1 thru A6, B1 thru B6, C1 thru C6, D1 thru D6\par
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3. header_10 PINS 1 THRU 10\par
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Note using the Allegro PCB Librarian XL tool (Flows > Library tools) Adding parts show both Concept symbol and Allegro symbol in Component browser viewer,\par
In project manager switch to Flows > Board Design to view schematic and board.\par
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Tool Version : Allegro PCB Librarian XL SPB 16.01\par
Platform and OS: WinXP\par
Testcase Structure\par
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1) libdev_archive \par
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2) buildlib\par
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3) schematic (Dummy root design) containing page border CADENCE_B SIZE PAGE and 3 sample connectors (versions 1 & 2 each)\par
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4) board (test.brd)\par
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4) This README file\par
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5) .cpm file\par
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Dependencies\par
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None\f1\par
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