I'm trying to implement this scenario on an AXI eVC slave agent:
           _   _   _   _   _   _   _   _   _   _   _   _   _
clk      _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
               ___         ___             ___
arvalid  _____| 1 |_______| 2 |___________| 3 |_______________
                           ___             ___
rvalid   _________________| 1 |___________| 2 |_______________

The scenario above is such that the current data phase (1), (2)
and the next address phase (2), (3) asserts at the same clock cycle.

I thought this code will do the trick:
extend MAIN vr_axi_slave_seq {
   body() @driver.clock is only {
      for i from 0 to 2 {
         do response keeping {
            for each (resp) in transfer_responses keep {
               resp.channel_delay == 0;
            };
         };
      };
   };
};

However, it seems that the AXI eVC slave agent, even if I constrain
channel_delay to 0, always behaves like this:

           _   _   _   _   _   _   _   _   _   _   _   _   _
clk      _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
               ___         ___             ___
arvalid  _____| 1 |_______| 2 |___________| 3 |_______________
                               ___             ___
rvalid   _____________________| 1 |___________| 2 |___________

Why is it that the AXI eVC slave agent seems to 'always' wait for
an address phase for it to start a data phase? Isn't it true
that the slave should be able to start data phase (2) without
waiting for address phase (3)?

What could be the possible cause for this?