Command line: /cad/cadence/spb/tools.lnx86/spectre/bin/32bit/spectre -env \ artist5.1.0 +escchars +log ../psf/spectre.out +inter=mpsc \ +mpssession=spectre0_7571_10 -format sst2 -raw ../psf \ +lqtimeout 900 -maxw 5 -maxn 5 input.scs spectre pid = 8674 Loading /cad/cadence/spb/tools.lnx86/cmi/lib/4.0/libinfineon_sh.so ... Loading /cad/cadence/spb/tools.lnx86/cmi/lib/4.0/libnortel_sh.so ... Loading /cad/cadence/spb/tools.lnx86/cmi/lib/4.0/libphilips_sh.so ... Loading /cad/cadence/spb/tools.lnx86/cmi/lib/4.0/libsparam_sh.so ... Loading /cad/cadence/spb/tools.lnx86/cmi/lib/4.0/libstmodels_sh.so ... spectre (ver. 6.0.2.119 -- 10 Nov 2005). Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. Simulating `input.scs' on vlsi58 at 4:28:22 PM, Thur Mar 17, 2011. Using new Spectre Parser. Auto-loading AHDL component. Finished loading AHDL component in 0 s (elapsed). Installed AHDL simulation interface. Opening directory input.ahdlSimDB/ (770) Opening directory input.ahdlSimDB/2814_Models_Spectre_._._MM180_RES_V133.va.ahdlcmi/ (770) Installed compiled interface for res_va. Opening directory input.ahdlSimDB/ (770) Opening directory input.ahdlSimDB/3528_Spectre_._._._mim.va.ahdlcmi/ (770) Installed compiled interface for mim_va. Opening directory input.ahdlSimDB/ (770) Opening directory input.ahdlSimDB/3528_Spectre_._._._resnp.va.ahdlcmi/ (770) Installed compiled interface for resnp_va. Opening directory input.ahdlSimDB/ (770) Opening directory input.ahdlSimDB/3528_Spectre_._._._respp.va.ahdlcmi/ (770) Installed compiled interface for respp_va. Opening directory input.ahdlSimDB/ (770) Opening directory input.ahdlSimDB/3528_Spectre_._._._reshr.va.ahdlcmi/ (770) Installed compiled interface for reshr_va. Opening directory input.ahdlSimDB/ (770) Opening directory input.ahdlSimDB/2526____Models_Spectre_._MM180_RES_V111.va.ahdlcmi/ (770) Installed compiled interface for res_nwell_va. Opening directory input.ahdlSimDB/ (770) Opening directory input.ahdlSimDB/input.ahdlcmi/ (770) Installed compiled interface for bsource_1. Warning from spectre during initial setup. I11.M0: `Pdiblc2' = -35.1181e-03 is negative. I11.M0: `Cdscd' = -500e-06 is negative. I11.M1: `Cdscd' = -28.83e-06 is negative. Error found by spectre during initial setup. Unable to open waveform file `/home/mudassar/UWB/BitStream/data/text.txt'. No such file or directory. Aggregate audit (4:28:23 PM, Thur Mar 17, 2011): Time used: CPU = 818 ms, elapsed = 1 s, util. = 81.8%. Virtual memory used = 12.7 Mbytes. spectre completes with 1 error, 3 warnings, and 0 notices. spectre terminated prematurely due to fatal error. //Input File format// 0.000000000000 0.000000000000 0.000000000040 0.000000000000 0.000000000080 0.000000000000 0.000000000120 0.000000000000 0.000000000160 0.000000000000 0.000000000200 0.000000000000 0.000000000240 0.000000000000 0.000000000280 0.000000000000 0.000000000320 0.000000000000 0.000000000360 0.000000000000 0.000000000400 0.000000000000 0.000000000440 0.000000000000 0.000000000480 0.000000000000 0.000000000520 0.000000000000 //input.scs file// // Generated for: spectre // Generated on: Mar 17 16:14:51 2011 // Design library name: UWB // Design cell name: test_1 // Design view name: schematic simulator lang=spectre global 0 vdd! include "/home/mudassar/UMC_18_CMOS/../Models/Spectre/MM180_SPECTRE_MAIN_V142.lib.scs" section=tt include "/home/mudassar/UMC_18_CMOS/../Models/Spectre/MM180_SPECTRE_MAIN_V142.lib.scs" section=diode include "/home/mudassar/UMC_18_CMOS/../Models/Spectre/MM180_SPECTRE_MAIN_V142.lib.scs" section=bjt include "/home/mudassar/UMC_18_CMOS/../Models/Spectre/MM180_SPECTRE_MAIN_V142.lib.scs" section=res_typ include "/home/mudassar/UMC_18_CMOS/../Models/Spectre/MM180_SPECTRE_MAIN_V142.lib.scs" section=mimcaps_typ include "/home/mudassar/UMC_18_CMOS/../Models/Spectre/MM180_SPECTRE_MAIN_V153.lib.scs" section=tt include "/home/mudassar/UMC_18_CMOS/../Models/Spectre/018-rf-v2d4-control.scs" include "/home/mudassar/UMC_18_CMOS/../Models/Spectre/MM180_RES_V111.lib.scs" section=res_typ // Library name: UWB // Cell name: Inverter // View name: schematic subckt Inverter GND IN OUT VDD M1 (OUT IN VDD VDD) p_18_mm w=1.2u l=180.0n ad=5.88e-13 as=5.88e-13 \ pd=3.38u ps=3.38u m=(1)*(1) M0 (OUT IN GND GND) n_18_mm w=400n l=180.0n ad=2.416e-13 as=2.416e-13 \ pd=2u ps=2u m=(1)*(1) ends Inverter // End of subcircuit definition. // Library name: UWB // Cell name: test_1 // View name: schematic I11 (0 net9 OUT vdd!) Inverter V1 (net9 0) vsource type=pwl m=100 noisevec=[ 1e8 0.2 1e9 0.1 ] \ file="/home/mudassar/UWB/BitStream/data/text.txt" V0 (vdd! 0) vsource dc=1.8 type=dc simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ checklimitdest=psf tran tran stop=1n errpreset=conservative write="spectre.ic" \ writefinal="spectre.fc" annotate=status maxiters=5 finalTimeOP info what=oppoint where=rawfile modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile saveOptions options save=allpub