library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
--use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

entity flip_flop_stimulus is

    generic(offset_time:integer:=100);

    port(
         clk: out std_logic;
         clk_inv: out std_logic;
         data: out std_logic;
	 data_inv: out std_logic

         --time_offset: in time
         -- time_range: in time
    );

end entity flip_flop_stimulus ;

architecture behavioral of flip_flop_stimulus is

  constant init_to_zero: boolean:= false; -- output Q is initialized to zero 
  constant probe_Q_pos_trans: boolean:= true;  -- rising edge of data & clk are similar in time
  constant sweep_left_to_right: boolean:= true; -- edge of data is swept from left to right over clock edge
  constant do_symmetric_sweep: boolean:= true; -- edge is sweept symmetrically around probe_at_time with given value of time_deflection
--  constant half_periode: time:= 3.125 ns / 2; -- 320 MHz clock
--  constant half_periode: time:= 781.25 ps / 2; -- 1.28 GHz clock
  constant half_periode: time:= 0.64 ns / 2; -- 1.5625 GHz MHz clock
  constant min_time_resolution: time:= 5 ps;
  constant time_deflection: time:= 1 ps * offset_time; -- time for which the edge is to be symmetrically be offset around probe_at_time
  constant probe_at_time: time:= -100 ps; -- set the time for which the edge of data should be swept symmetrically around it
--  constant time_offset: time:= 0 ps;

  constant num_of_diversions: integer:= time_deflection/min_time_resolution;

  signal int_clk: std_logic;
  signal int_data: std_logic;

begin 

   clk <= int_clk;
   clk_inv <= not int_clk;
   data <= int_data;
   data_inv <= not int_data;

  clkgen:process
  begin
    int_clk<='0';
    wait for half_periode;
    int_clk<='1';
    wait for half_periode;
  end process clkgen;

  datagen:process
  variable j: integer:= 0;
  begin


    for i in -num_of_diversions to num_of_diversions loop

      if sweep_left_to_right then
        j:=i;
      else
        j:=-i;
      end if;

      wait until int_clk='0'; -- wait on clk is '0' to start
      
      if (init_to_zero) then
        int_data <= '0';
      else
        int_data <= '1';
      end if;

      wait until int_clk='1'; -- wait to let the flip-flop initialize

      if (probe_Q_pos_trans) then
	int_data <= '0' after half_periode/2;
      else
        int_data <= '1' after half_periode/2;
      end if;

      wait until int_clk='0'; -- wait until falling edge to be assure int_data is set correct

      int_data <= not int_data after (half_periode + probe_at_time + j*min_time_resolution);
		
      wait until int_clk='1';

    end loop;

    wait;

  end process datagen;

end architecture behavioral;