// Generated for: spectre
// Generated on: May 27 14:57:43 2013
// Design library name: test
// Design cell name: test-circuit-model3
// Design view name: schematic
simulator lang=spectre
global 0

// Library name: SPADmodels
// Cell name: model3
// View name: schematic
subckt model3 anode cathode photon substrate
    I4 (net26 anode Meetpunt cathode anode) pwlvsres
    Vf (net1 net20) vsource dc=900.0m type=dc
    Vr (net3 net16) vsource dc=35 type=dc
    Cac (cathode anode) capacitor c=1.75p
    Ccs (cathode substrate) capacitor c=770.00f
    Cas (substrate anode) capacitor c=2.35p
    W7 (net061 net060 \+ \-) relay ropen=1T rclosed=1.0
    W5 (net16 anode net16 anode) relay vt1=0 ropen=1T rclosed=1.0 \
        region=off
    W4 (anode net1 anode net1) relay vt1=0 ropen=1T rclosed=1.0 region=on
    W3 (net26 net092 cathode net092) relay vt1=100u ropen=1T rclosed=1m
    Strig (net092 net26 Vtrigger 0) relay vt1=2 ropen=1T rclosed=1u
    S1 (Vtrigger 0 anode cathode) relay vt1=-21.54 ropen=1T rclosed=1.0
    S2 (Vtrigger 0 cathode anode) relay vt1=35 ropen=1T rclosed=1.0
    Rsense (cathode net092) resistor r=1
    Rf (cathode net20) resistor r=47
    Rr (cathode net3) resistor r=100
    R1 (Vtrigger 0) resistor r=1K
    R2 (photon Vtrigger) resistor r=1K
ends model3
// End of subcircuit definition.

// Library name: test
// Cell name: test-circuit-model3
// View name: schematic
V2 (Vin 0) vsource type=pwl wave=[ 0 20 10u 25 ]
I6 (0 Vin Vphoton 0) model3
V1 (Vphoton 0) vsource type=pulse val0=0 val1=10 period=2u delay=500.0n \
        rise=10p fall=10p width=1u
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf 
tran tran stop=10u write="spectre.ic" writefinal="spectre.fc" \
    annotate=status maxiters=5 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
saveOptions options save=allpub
ahdl_include "/misc/icenas/s1127446/cadence/SPADmodels/pwlvsres/veriloga/veriloga.va"