******************************************************************************* ****** inverter schematic inverter_test inverter layout inverter_test ******************************************************************************* Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet, nfet) Generic 1 1 (subc, subc) Generic 1 1 (pfet, pfet) Generic 1 1 ------ ------ Total 3 3 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) Generic 0 0 0 0 (nfet_m0) Generic 1 1 1 1 (pfet) Generic 0 0 0 0 (pfet_m0) Generic 1 1 1 1 (subc) Generic 1 1 1 1 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) Generic 0 0 0 0 (nfet_m0) Generic 1 1 1 1 (pfet) Generic 0 0 0 0 (pfet_m0) Generic 1 1 1 1 (subc) Generic 1 1 1 1 Match Statistics ================ Total Unmatched Cell/Device schematic layout schematic layout (nfet) Generic 0 0 0 0 (nfet_m0) Generic 1 1 0 0 (pfet) Generic 0 0 0 0 (pfet_m0) Generic 1 1 0 0 (subc) Generic 1 1 0 0 ------ ------ ------ ------ Total 3 3 0 0 Match Statistics for Nets 5 5 0 0 =====================================================================[inverter] ====== Bad Initial Net Bindings (nets don't match) ============================ =============================================================================== = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badbind 1) Schematic Net: vdd S *1 of pfet_m0 S S *1 of pfet_m0 B Layout Net: vdd L *1 of pfet_m0 D L *1 of pfet_m0 B = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badbind 2) Schematic Net: vout S *1 of pfet_m0 D S *1 of nfet_m0 D Layout Net: vout L *1 of pfet_m0 S L *1 of nfet_m0 D =====================================================================[inverter] ====== Suggested Terminal Rewire ============================================== =============================================================================== In the layout, terminal 'S' of instance avD3103_1 probably should connect to net vdd instead of net vout. This makes a better match between layout net vdd and schematic net vdd. In the layout, terminal 'D' of instance avD3103_1 probably should connect to net vout instead of net vdd. This makes a better match between layout net vout and schematic net vout. =====================================================================[inverter] ====== Problem Schematic Nets (no exact match in layout) ====================== =============================================================================== S S ?vout S 1 of pfet_m0 D S 1 of nfet_m0 D S S ?vdd S 1 of pfet_m0 S S 1 of pfet_m0 B =====================================================================[inverter] ====== Problem Layout Nets (no exact match in schematic) ====================== =============================================================================== L L ?vdd L 1 of pfet_m0 D L 1 of pfet_m0 B L L ?vout L 1 of pfet_m0 S L 1 of nfet_m0 D =====================================================================[inverter] ====== Matched Instances with Bad Net Connections ============================= =============================================================================== = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badcon 1) Schematic Instance: TP0 pfet_m0 Layout Instance: avD3103_1 pfet_m0 Pin SchNet : LayNet --- ------ : ------ D vout : vdd S vdd : vout =====================================================================[inverter] ====== Summary of Errors ====================================================== =============================================================================== Schematic Layout Error Type --------- ------ ---------- 2 2 Bad Initial Net Bindings - 2 Suggested Terminal Rewire 1 1 Matched Instances with Bad Net Connections