======================================================================== ====File: refleks_switcher.err ======================================================================== ======================================================================== ====File: refleks_switcher.csm ======================================================================== Schematic | Layout | Status ------------------------------------------------------------------------------- DFF_E | DFF_E layout r_test4 | expanded DFF_E | DFF_E_VAR1 layout r_test4 | expanded NOR2_E | NOR2_E layout r_test4 | expanded NOR2_E | NOR2_E_VAR1 layout r_test4 | matched NOR2_E | NOR2_E_VAR2 layout r_test4 | expanded INVERTBAL_E | INVERTBAL_E layout r_test4 | expanded INVERTBAL_H | INVERTBAL_H layout r_test4 | expanded INVERTBAL_H | INVERTBAL_H_VAR1 layout r_test4 | matched MUX21I_D | MUX21I_D layout r_test4 | matched OA21_I | OA21_I layout r_test4 | expanded OAI21_C | OAI21_C layout r_test4 | matched AND4_E | AND4_E layout r_test4 | matched AO22_B | AO22_B layout r_test4 | expanded OR4_E | OR4_E layout r_test4 | matched AND2_F | AND2_F layout r_test4 | expanded NAND2_F | NAND2_F layout r_test4 | expanded NAND2_F | NAND2_F_VAR1 layout r_test4 | expanded INVERT_I | INVERT_I layout r_test4 | expanded NOR2_D | NOR2_D layout r_test4 | expanded NOR2_D | NOR2_D_VAR2 layout r_test4 | expanded NOR2_D | NOR2_D_VAR3 layout r_test4 | expanded XOR2_C | XOR2_C layout r_test4 | expanded XOR2_C | XOR2_C_VAR1 layout r_test4 | expanded XOR2_C | XOR2_C_VAR2 layout r_test4 | expanded INVERT_H | INVERT_H layout r_test4 | matched XNOR2_C | XNOR2_C layout r_test4 | expanded INVERT_E | INVERT_E layout r_test4 | matched OR2_I | OR2_I layout r_test4 | matched AOI21_C | AOI21_C layout r_test4 | expanded INVERT_F | INVERT_F layout r_test4 | expanded refleks_switcher | refleks_switcher layout r_test4 | errors * Mismatch between Schematic and Layout 1 cell with errors 21 cells expanded 9 cells matched ======================================================================== ====File: refleks_switcher.cls ======================================================================== ############################################################################### ###### DFF_E DFF_E layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 12 12 (pfet) MOS 12 12 ------ ------ Total 24 24 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 12 12 12 12 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 12 12 12 12 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 12 12 12 12 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 12 12 12 12 ------ ------ ------ ------ Total 24 24 24 24 ############################################################################### ###### DFF_E DFF_E_VAR1 layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 12 12 (pfet) MOS 12 12 ------ ------ Total 24 24 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 12 12 12 12 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 12 12 12 12 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 12 12 12 12 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 12 12 12 12 ------ ------ ------ ------ Total 24 24 24 24 ############################################################################### ###### NOR2_E NOR2_E layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 2 2 (pfet) MOS 4 4 ------ ------ Total 6 6 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 ------ ------ ------ ------ Total 6 6 6 6 ******************************************************************************* ****** NOR2_E NOR2_E_VAR1 layout r_test4 ******************************************************************************* Filter/Reduce statistics only. Network matching was OK. Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 2 2 (pfet) MOS 4 4 ------ ------ Total 6 6 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 ------ ------ ------ ------ Total 6 6 6 6 ############################################################################### ###### NOR2_E NOR2_E_VAR2 layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 2 2 (pfet) MOS 4 4 ------ ------ Total 6 6 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 ------ ------ ------ ------ Total 6 6 6 6 ############################################################################### ###### INVERTBAL_E INVERTBAL_E layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 2 2 (pfet) MOS 2 2 ------ ------ Total 4 4 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 2 2 2 2 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 1 1 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 2 2 1 1 ------ ------ ------ ------ Total 4 4 2 2 ############################################################################### ###### INVERTBAL_H INVERTBAL_H layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 2 2 (pfet) MOS 2 2 ------ ------ Total 4 4 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 2 2 2 2 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 1 1 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 2 2 1 1 ------ ------ ------ ------ Total 4 4 2 2 ******************************************************************************* ****** INVERTBAL_H INVERTBAL_H_VAR1 layout r_test4 ******************************************************************************* Filter/Reduce statistics only. Network matching was OK. Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 2 2 (pfet) MOS 2 2 ------ ------ Total 4 4 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 2 2 2 2 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 1 1 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 2 2 1 1 ------ ------ ------ ------ Total 4 4 2 2 ******************************************************************************* ****** MUX21I_D MUX21I_D layout r_test4 ******************************************************************************* Filter/Reduce statistics only. Network matching was OK. Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 5 5 (pfet) MOS 5 5 ------ ------ Total 10 10 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 5 5 5 5 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 5 5 5 5 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 5 5 5 5 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 5 5 5 5 ------ ------ ------ ------ Total 10 10 10 10 ############################################################################### ###### OA21_I OA21_I layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 6 6 (pfet) MOS 5 5 ------ ------ Total 11 11 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 6 6 6 6 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 5 5 5 5 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 6 6 5 5 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 5 5 4 4 ------ ------ ------ ------ Total 11 11 9 9 ******************************************************************************* ****** OAI21_C OAI21_C layout r_test4 ******************************************************************************* Filter/Reduce statistics only. Network matching was OK. Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 4 4 (pfet) MOS 3 3 ------ ------ Total 7 7 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 4 4 4 4 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 3 3 3 3 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 4 4 4 4 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 3 3 3 3 ------ ------ ------ ------ Total 7 7 7 7 ******************************************************************************* ****** AND4_E AND4_E layout r_test4 ******************************************************************************* Filter/Reduce statistics only. Network matching was OK. Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 5 5 (pfet) MOS 5 5 ------ ------ Total 10 10 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 5 5 5 5 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 5 5 5 5 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 5 5 5 5 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 5 5 5 5 ------ ------ ------ ------ Total 10 10 10 10 ############################################################################### ###### AO22_B AO22_B layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 5 5 (pfet) MOS 5 5 ------ ------ Total 10 10 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 5 5 5 5 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 5 5 5 5 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 5 5 5 5 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 5 5 5 5 ------ ------ ------ ------ Total 10 10 10 10 ******************************************************************************* ****** OR4_E OR4_E layout r_test4 ******************************************************************************* Filter/Reduce statistics only. Network matching was OK. Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 5 5 (pfet) MOS 5 5 ------ ------ Total 10 10 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 5 5 5 5 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 5 5 5 5 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 5 5 5 5 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 5 5 5 5 ------ ------ ------ ------ Total 10 10 10 10 ############################################################################### ###### AND2_F AND2_F layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 3 3 (pfet) MOS 3 3 ------ ------ Total 6 6 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 3 3 3 3 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 3 3 3 3 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 3 3 3 3 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 3 3 3 3 ------ ------ ------ ------ Total 6 6 6 6 ############################################################################### ###### NAND2_F NAND2_F layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 4 4 (pfet) MOS 4 4 ------ ------ Total 8 8 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 4 4 4 4 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 4 4 4 4 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 2 2 ------ ------ ------ ------ Total 8 8 6 6 ############################################################################### ###### NAND2_F NAND2_F_VAR1 layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 4 4 (pfet) MOS 4 4 ------ ------ Total 8 8 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 4 4 4 4 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 4 4 4 4 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 2 2 ------ ------ ------ ------ Total 8 8 6 6 ############################################################################### ###### INVERT_I INVERT_I layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 2 2 (pfet) MOS 2 2 ------ ------ Total 4 4 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 2 2 2 2 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 1 1 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 2 2 1 1 ------ ------ ------ ------ Total 4 4 2 2 ############################################################################### ###### NOR2_D NOR2_D layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 2 2 (pfet) MOS 4 4 ------ ------ Total 6 6 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 ------ ------ ------ ------ Total 6 6 6 6 ############################################################################### ###### NOR2_D NOR2_D_VAR2 layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 2 2 (pfet) MOS 4 4 ------ ------ Total 6 6 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 ------ ------ ------ ------ Total 6 6 6 6 ############################################################################### ###### NOR2_D NOR2_D_VAR3 layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 2 2 (pfet) MOS 4 4 ------ ------ Total 6 6 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 ------ ------ ------ ------ Total 6 6 6 6 ############################################################################### ###### XOR2_C XOR2_C layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 5 5 (pfet) MOS 4 4 ------ ------ Total 9 9 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 5 5 5 5 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 5 5 5 5 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 ------ ------ ------ ------ Total 9 9 9 9 ############################################################################### ###### XOR2_C XOR2_C_VAR1 layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 5 5 (pfet) MOS 4 4 ------ ------ Total 9 9 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 5 5 5 5 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 5 5 5 5 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 ------ ------ ------ ------ Total 9 9 9 9 ############################################################################### ###### XOR2_C XOR2_C_VAR2 layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 5 5 (pfet) MOS 4 4 ------ ------ Total 9 9 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 5 5 5 5 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 5 5 5 5 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 ------ ------ ------ ------ Total 9 9 9 9 ******************************************************************************* ****** INVERT_H INVERT_H layout r_test4 ******************************************************************************* Filter/Reduce statistics only. Network matching was OK. Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 2 2 (pfet) MOS 2 2 ------ ------ Total 4 4 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 2 2 2 2 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 1 1 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 2 2 1 1 ------ ------ ------ ------ Total 4 4 2 2 ############################################################################### ###### XNOR2_C XNOR2_C layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 4 4 (pfet) MOS 5 5 ------ ------ Total 9 9 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 4 4 4 4 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 5 5 5 5 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 4 4 4 4 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 5 5 5 5 ------ ------ ------ ------ Total 9 9 9 9 ******************************************************************************* ****** INVERT_E INVERT_E layout r_test4 ******************************************************************************* Filter/Reduce statistics only. Network matching was OK. Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 1 1 (pfet) MOS 1 1 ------ ------ Total 2 2 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 1 1 1 1 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 1 1 1 1 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 1 1 1 1 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 1 1 1 1 ------ ------ ------ ------ Total 2 2 2 2 ******************************************************************************* ****** OR2_I OR2_I layout r_test4 ******************************************************************************* Filter/Reduce statistics only. Network matching was OK. Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 4 4 (pfet) MOS 4 4 ------ ------ Total 8 8 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 4 4 4 4 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 4 4 3 3 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 3 3 ------ ------ ------ ------ Total 8 8 6 6 ############################################################################### ###### AOI21_C AOI21_C layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 3 3 (pfet) MOS 4 4 ------ ------ Total 7 7 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 3 3 3 3 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 3 3 3 3 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 4 4 4 4 ------ ------ ------ ------ Total 7 7 7 7 ############################################################################### ###### INVERT_F INVERT_F layout r_test4 ############################################################################### ###### This report is for informational purposes only. This cell ###### has been expanded because of unstable instance parameter values. ############################################################################### Pre-expand Statistics ====================== Original Cell/Device schematic layout (nfet) MOS 2 2 (pfet) MOS 2 2 ------ ------ Total 4 4 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 2 2 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 2 2 2 2 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (nfet) MOS 0 0 0 0 (nfet_m0) MOS 2 2 1 1 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 2 2 1 1 ------ ------ ------ ------ Total 4 4 2 2 ******************************************************************************* ****** refleks_switcher refleks_switcher layout r_test4 ******************************************************************************* Pre-expand Statistics ====================== Original Cell/Device schematic layout (dff, _) Cell 1 0* (dff_65, _) Cell 1 0* (dff_64, _) Cell 1 0* (OA21_I) Cell 2 2 (NOR2_E) Cell 6 5* (OAI21_C) Cell 1 1 (AND4_E) Cell 1 1 (AO22_B) Cell 8 8 (OR4_E) Cell 1 1 (AND2_F) Cell 2 2 (NAND2_F) Cell 11 7* (INVERT_I) Cell 2 2 (INVERTBAL_E) Cell 1 2* (DFF_E) Cell 16 16 (NOR2_D) Cell 14 9* (XOR2_C) Cell 11 5* (INVERT_H) Cell 2 2 (XNOR2_C) Cell 3 3 (INVERT_E) Cell 2 2 (INVERTBAL_H) Cell 2 2 (OR2_I) Cell 1 1 (AOI21_C) Cell 2 2 (INVERT_F) Cell 2 2 (_, FILL1 layout r_test4) Cell 0 11* (_, FILL2 layout r_test4) Cell 0 13* (MUX21I_D, MUX21I_D layout r_test4) Cell 0 1* (_, NWSX layout r_test4) Cell 0 83* (_, refleks_switcher_VIA0 layout ...) Cell 0 8* (_, refleks_switcher_VIA2 layout ...) Cell 0 2* ------ ------ Total 93 193 Filter Statistics ================= Original Filtered Cell/Device schematic layout schematic layout (AND4_E) Cell 1 1 1 1 (INVERT_E) Cell 2 2 2 2 (INVERT_H) Cell 2 2 2 2 (MUX21I_D) Cell 1 1 1 1 (OAI21_C) Cell 1 1 1 1 (OR2_I) Cell 1 1 1 1 (OR4_E) Cell 1 1 1 1 (nfet) MOS 0 0 0 0 (nfet_m0) MOS 467 467 467 467 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 505 505 505 505 Reduce Statistics ================= Filtered Reduced Cell/Device schematic layout schematic layout (AND4_E) Cell 1 1 1 1 (INVERT_E) Cell 2 2 2 2 (INVERT_H) Cell 2 2 2 2 (MUX21I_D) Cell 1 1 1 1 (OAI21_C) Cell 1 1 1 1 (OR2_I) Cell 1 1 1 1 (OR4_E) Cell 1 1 1 1 (nfet) MOS 0 0 0 0 (nfet_m0) MOS 467 467 456 456 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 505 505 472 472 Match Statistics ================ Total Unmatched Cell/Device schematic layout schematic layout (AND4_E) Cell 1 1 0 0 (INVERT_E) Cell 2 2 0 0 (INVERT_H) Cell 2 2 0 0 (MUX21I_D) Cell 1 1 0 0 (OAI21_C) Cell 1 1 0 0 (OR2_I) Cell 1 1 0 0 (OR4_E) Cell 1 1 0 0 (nfet) MOS 0 0 0 0 (nfet_m0) MOS 456 456 0 0 (pfet) MOS 0 0 0 0 (pfet_m0) MOS 472 472 0 0 ------ ------ ------ ------ Total 937 937 0 0 Match Statistics for Nets 686 508 180 2 =============================================================[refleks_switcher] ====== Unbound Pin ============================================================ =============================================================================== S clk S rst S pwm_in_port1[7] S pwm_in_port1[6] S pwm_in_port1[4] S pwm_in_port1[3] S pwm_in_port1[2] S pwm_in_port1[0] S pwm_in_port2[7] S pwm_in_port2[6] S pwm_in_port2[5] S pwm_in_port2[4] S pwm_in_port2[3] S pwm_in_port2[1] S pwm_in_port2[0] S pwm_ctrl S pwm_out[7] S pwm_out[6] S pwm_out[5] S pwm_out[4] S pwm_out[3] S pwm_out[0] =============================================================[refleks_switcher] ====== Shorted Instance Connections =========================================== =============================================================================== Layout net: GND! shorts to I__13/GND! Layout net: GND! shorts to I__62/GND! Layout net: GND! shorts to I__78/GND! Layout net: GND! shorts to I__51/GND! Layout net: GND! shorts to I__44/GND! Layout net: GND! shorts to I__8/GND! Layout net: GND! shorts to I__12/GND! Layout net: GND! shorts to I__86/GND! Layout net: GND! shorts to I__22/GND! Layout net: VDD! shorts to I__13/VDD! Layout net: VDD! shorts to I__62/VDD! Layout net: VDD! shorts to I__78/VDD! Layout net: VDD! shorts to I__51/VDD! Layout net: VDD! shorts to I__44/VDD! Layout net: VDD! shorts to I__8/VDD! Layout net: VDD! shorts to I__12/VDD! Layout net: VDD! shorts to I__86/VDD! Layout net: VDD! shorts to I__22/VDD! =============================================================[refleks_switcher] ====== Unmatched Internal Nets ================================================ =============================================================================== S ?pwm_ctrl_reg0/q_reg/GND! S ?pwm_ctrl_reg0/q_reg/VDD! S ?pwm_ctrl_reg0/g8/GND! S ?pwm_ctrl_reg0/g8/VDD! S ?pwm_ctrl_reg0/g7/GND! S ?pwm_ctrl_reg0/g7/VDD! S ?pwm_ctrl_reg1/q_reg/GND! S ?pwm_ctrl_reg1/q_reg/VDD! S ?pwm_ctrl_reg1/g8/GND! S ?pwm_ctrl_reg1/g8/VDD! S ?pwm_ctrl_reg1/g7/GND! S ?pwm_ctrl_reg1/g7/VDD! S ?pwm_mux_reg/q_reg/GND! S ?pwm_mux_reg/q_reg/VDD! S ?pwm_mux_reg/g7/GND! S ?pwm_mux_reg/g7/VDD! S ?g500/GND! S ?g500/VDD! S ?g750/GND! S ?g750/VDD! S ?g490/GND! S ?g490/VDD! S ?g491/GND! S ?g491/VDD! S ?g492/GND! S ?g492/VDD! S ?g493/GND! S ?g493/VDD! S ?g494/GND! S ?g494/VDD! S ?g495/GND! S ?g495/VDD! S ?g496/GND! S ?g496/VDD! S ?g497/GND! S ?g497/VDD! S ?g754/GND! S ?g754/VDD! S ?g756/GND! S ?g756/VDD! S ?\pwm_ctrl_counter_value_s_reg[13]/GND! S ?\pwm_ctrl_counter_value_s_reg[13]/VDD! S ?\pwm_ctrl_counter_value_s_reg[12]/GND! S ?\pwm_ctrl_counter_value_s_reg[12]/VDD! S ?\pwm_ctrl_counter_value_s_reg[11]/GND! S ?\pwm_ctrl_counter_value_s_reg[11]/VDD! S ?\pwm_ctrl_counter_value_s_reg[9]/GND! S ?\pwm_ctrl_counter_value_s_reg[9]/VDD! S ?\pwm_ctrl_counter_value_s_reg[10]/GND! S ?\pwm_ctrl_counter_value_s_reg[10]/VDD! S ?\pwm_ctrl_counter_value_s_reg[8]/GND! S ?\pwm_ctrl_counter_value_s_reg[8]/VDD! S ?\pwm_ctrl_counter_value_s_reg[7]/GND! S ?\pwm_ctrl_counter_value_s_reg[7]/VDD! S ?\pwm_ctrl_counter_value_s_reg[5]/GND! S ?\pwm_ctrl_counter_value_s_reg[5]/VDD! S ?\pwm_ctrl_counter_value_s_reg[6]/GND! S ?\pwm_ctrl_counter_value_s_reg[6]/VDD! S ?\pwm_ctrl_counter_value_s_reg[4]/GND! S ?\pwm_ctrl_counter_value_s_reg[4]/VDD! S ?\pwm_ctrl_counter_value_s_reg[3]/GND! S ?\pwm_ctrl_counter_value_s_reg[3]/VDD! S ?\pwm_ctrl_counter_value_s_reg[2]/GND! S ?\pwm_ctrl_counter_value_s_reg[2]/VDD! S ?\pwm_ctrl_counter_value_s_reg[1]/GND! S ?\pwm_ctrl_counter_value_s_reg[1]/VDD! S ?\pwm_ctrl_counter_value_s_reg[0]/GND! S ?\pwm_ctrl_counter_value_s_reg[0]/VDD! S ?\ctrl_current_reg[0]/GND! S ?\ctrl_current_reg[0]/VDD! S ?\ctrl_current_reg[1]/GND! S ?\ctrl_current_reg[1]/VDD! S ?g503/GND! S ?g503/VDD! S ?g729/GND! S ?g729/VDD! S ?g755/GND! S ?g755/VDD! S ?g758/GND! S ?g758/VDD! S ?g772/GND! S ?g772/VDD! S ?g502/GND! S ?g502/VDD! S ?g764/GND! S ?g764/VDD! S ?g501/GND! S ?g501/VDD! S ?g700/GND! S ?g700/VDD! S ?g706/GND! S ?g706/VDD! S ?g713/GND! S ?g713/VDD! S ?g717/GND! S ?g717/VDD! S ?g724/GND! S ?g724/VDD! S ?g730/GND! S ?g730/VDD! S ?g737/GND! S ?g737/VDD! S ?g743/GND! S ?g743/VDD! S ?g753/GND! S ?g753/VDD! S ?g759/GND! S ?g759/VDD! S ?g691/GND! S ?g691/VDD! S ?g693/GND! S ?g693/VDD! S ?g697/GND! S ?g697/VDD! S ?g701/GND! S ?g701/VDD! S ?g702/GND! S ?g702/VDD! S ?g707/GND! S ?g707/VDD! S ?g714/GND! S ?g714/VDD! S ?g719/GND! S ?g719/VDD! S ?g720/GND! S ?g720/VDD! S ?g725/GND! S ?g725/VDD! S ?g731/GND! S ?g731/VDD! S ?g738/GND! S ?g738/VDD! S ?g744/GND! S ?g744/VDD! S ?g745/GND! S ?g745/VDD! S ?g487/GND! S ?g487/VDD! S ?g499/GND! S ?g499/VDD! S ?g718/GND! S ?g718/VDD! S ?g736/GND! S ?g736/VDD! S ?g748/GND! S ?g748/VDD! S ?g749/GND! S ?g749/VDD! S ?g485/GND! S ?g485/VDD! S ?g486/GND! S ?g486/VDD! S ?g709/GND! S ?g709/VDD! S ?g2/GND! S ?g2/VDD! S ?g779/GND! S ?g779/VDD! S ?g694/GND! S ?g694/VDD! S ?g698/GND! S ?g698/VDD! S ?g703/GND! S ?g703/VDD! S ?g708/GND! S ?g708/VDD! S ?g715/GND! S ?g715/VDD! S ?g721/GND! S ?g721/VDD! S ?g726/GND! S ?g726/VDD! S ?g732/GND! S ?g732/VDD! S ?g746/GND! S ?g746/VDD! S ?g752/GND! S ?g752/VDD! S ?g757/GND! S ?g757/VDD! =============================================================[refleks_switcher] ====== Problem Schematic Nets (no exact match in layout) ====================== =============================================================================== S S ?pwm_ctrl_reg0/g8/GND! ?pwm_ctrl_reg1/g8/GND! ?g503/GND! ?g729/GND! S ?g755/GND! ?g758/GND! ?g772/GND! ?g502/GND! ?g764/GND! S (total 9) with: S 1 of nfet_m0 {D S} S 1 of nfet_m0 B S S ?pwm_ctrl_reg0/g7/GND! ?pwm_ctrl_reg1/g7/GND! ?pwm_mux_reg/g7/GND! ?g691/GND! S ?g693/GND! ?g697/GND! ?g701/GND! ?g702/GND! ?g707/GND! ?g714/GND! ?g719/GND! S ?g720/GND! ?g725/GND! ?g731/GND! ?g738/GND! ?g744/GND! ?g745/GND! ?g487/GND! S ?g499/GND! ?g718/GND! ?g736/GND! ?g748/GND! ?g749/GND! S (total 23) with: S 2 of nfet_m0 {D S} S 2 of nfet_m0 B S S ?g500/GND! ?g750/GND! ?g754/GND! ?g756/GND! S (total 4) with: S 2 of nfet_m0 {D S} S 3 of nfet_m0 B S S ?g501/GND! ?g700/GND! ?g706/GND! ?g713/GND! ?g717/GND! ?g724/GND! ?g730/GND! S ?g737/GND! ?g743/GND! ?g753/GND! ?g759/GND! ?g709/GND! ?g2/GND! ?g779/GND! S (total 14) with: S 2 of nfet_m0 {D S} S 4 of nfet_m0 B S S ?g490/GND! ?g491/GND! ?g492/GND! ?g493/GND! ?g494/GND! ?g495/GND! ?g496/GND! S ?g497/GND! ?g485/GND! ?g486/GND! ?g694/GND! ?g698/GND! ?g703/GND! ?g708/GND! S ?g715/GND! ?g721/GND! ?g726/GND! ?g732/GND! ?g746/GND! ?g752/GND! ?g757/GND! S (total 21) with: S 3 of nfet_m0 {D S} S 5 of nfet_m0 B S S ?pwm_ctrl_reg0/q_reg/GND! ?pwm_ctrl_reg1/q_reg/GND! ?pwm_mux_reg/q_reg/GND! S ?\pwm_ctrl_counter_value_s_reg[13]/GND! S ?\pwm_ctrl_counter_value_s_reg[12]/GND! S ?\pwm_ctrl_counter_value_s_reg[11]/GND! S ?\pwm_ctrl_counter_value_s_reg[9]/GND! S ?\pwm_ctrl_counter_value_s_reg[10]/GND! S ?\pwm_ctrl_counter_value_s_reg[8]/GND! S ?\pwm_ctrl_counter_value_s_reg[7]/GND! S ?\pwm_ctrl_counter_value_s_reg[5]/GND! S ?\pwm_ctrl_counter_value_s_reg[6]/GND! S ?\pwm_ctrl_counter_value_s_reg[4]/GND! S ?\pwm_ctrl_counter_value_s_reg[3]/GND! S ?\pwm_ctrl_counter_value_s_reg[2]/GND! S ?\pwm_ctrl_counter_value_s_reg[1]/GND! S ?\pwm_ctrl_counter_value_s_reg[0]/GND! ?\ctrl_current_reg[0]/GND! S ?\ctrl_current_reg[1]/GND! S (total 19) with: S 8 of nfet_m0 {D S} S 12 of nfet_m0 B S S ?pwm_ctrl_reg0/g8/VDD! ?pwm_ctrl_reg1/g8/VDD! ?g503/VDD! ?g729/VDD! S ?g755/VDD! ?g758/VDD! ?g772/VDD! ?g502/VDD! ?g764/VDD! S (total 9) with: S 1 of pfet_m0 {D S} S 1 of pfet_m0 B S S ?g501/VDD! ?g700/VDD! ?g706/VDD! ?g713/VDD! ?g717/VDD! ?g724/VDD! ?g730/VDD! S ?g737/VDD! ?g743/VDD! ?g753/VDD! ?g759/VDD! S (total 11) with: S 2 of pfet_m0 {D S} S 2 of pfet_m0 B S S ?pwm_ctrl_reg0/g7/VDD! ?pwm_ctrl_reg1/g7/VDD! ?pwm_mux_reg/g7/VDD! ?g754/VDD! S ?g756/VDD! ?g691/VDD! ?g693/VDD! ?g697/VDD! ?g701/VDD! ?g702/VDD! ?g707/VDD! S ?g714/VDD! ?g719/VDD! ?g720/VDD! ?g725/VDD! ?g731/VDD! ?g738/VDD! ?g744/VDD! S ?g745/VDD! ?g487/VDD! ?g499/VDD! ?g718/VDD! ?g736/VDD! ?g748/VDD! ?g749/VDD! S ?g694/VDD! ?g698/VDD! ?g703/VDD! ?g708/VDD! ?g715/VDD! ?g721/VDD! ?g726/VDD! S ?g732/VDD! ?g746/VDD! ?g752/VDD! ?g757/VDD! S (total 36) with: S 2 of pfet_m0 {D S} S 4 of pfet_m0 B S S ?g500/VDD! ?g750/VDD! S (total 2) with: S 3 of pfet_m0 {D S} S 3 of pfet_m0 B S S ?g485/VDD! ?g486/VDD! S (total 2) with: S 3 of pfet_m0 {D S} S 4 of pfet_m0 B S S ?g490/VDD! ?g491/VDD! ?g492/VDD! ?g493/VDD! ?g494/VDD! ?g495/VDD! ?g496/VDD! S ?g497/VDD! ?g709/VDD! ?g2/VDD! ?g779/VDD! S (total 11) with: S 3 of pfet_m0 {D S} S 5 of pfet_m0 B S S ?pwm_ctrl_reg0/q_reg/VDD! ?pwm_ctrl_reg1/q_reg/VDD! ?pwm_mux_reg/q_reg/VDD! S ?\pwm_ctrl_counter_value_s_reg[13]/VDD! S ?\pwm_ctrl_counter_value_s_reg[12]/VDD! S ?\pwm_ctrl_counter_value_s_reg[11]/VDD! S ?\pwm_ctrl_counter_value_s_reg[9]/VDD! S ?\pwm_ctrl_counter_value_s_reg[10]/VDD! S ?\pwm_ctrl_counter_value_s_reg[8]/VDD! S ?\pwm_ctrl_counter_value_s_reg[7]/VDD! S ?\pwm_ctrl_counter_value_s_reg[5]/VDD! S ?\pwm_ctrl_counter_value_s_reg[6]/VDD! S ?\pwm_ctrl_counter_value_s_reg[4]/VDD! S ?\pwm_ctrl_counter_value_s_reg[3]/VDD! S ?\pwm_ctrl_counter_value_s_reg[2]/VDD! S ?\pwm_ctrl_counter_value_s_reg[1]/VDD! S ?\pwm_ctrl_counter_value_s_reg[0]/VDD! ?\ctrl_current_reg[0]/VDD! S ?\ctrl_current_reg[1]/VDD! S (total 19) with: S 8 of pfet_m0 {D S} S 12 of pfet_m0 B =============================================================[refleks_switcher] ====== Problem Layout Nets (no exact match in schematic) ====================== =============================================================================== L L ?VDD! L 1 of AND4_E ?VDD! L 2 of INVERT_E ?VDD! L 2 of INVERT_H ?VDD! L 1 of MUX21I_D ?VDD! L 1 of OAI21_C ?VDD! L 1 of OR2_I ?VDD! L 1 of OR4_E ?VDD! L 300 of pfet_m0 {D S} L 472 of pfet_m0 B L L ?GND! L 1 of AND4_E ?GND! L 2 of INVERT_E ?GND! L 2 of INVERT_H ?GND! L 1 of MUX21I_D ?GND! L 1 of OAI21_C ?GND! L 1 of OR2_I ?GND! L 1 of OR4_E ?GND! L 306 of nfet_m0 {D S} L 456 of nfet_m0 B =============================================================[refleks_switcher] ====== Summary of Errors ====================================================== =============================================================================== Schematic Layout Error Type --------- ------ ---------- 180 - Unmatched Internal Nets - 18 Shorted Instance Connections 22 - Unbound Pin ======================================================================== ====File: refleks_switcher.cps ======================================================================== ; autoPinSwap() results for schematic network. swapPins("MUX21I_D" "") swapPins("OAI21_C" "") swapPins("AND4_E" "") swapPins("OR4_E" "") swapPins("INVERT_H" "") swapPins("INVERT_E" "") swapPins("OR2_I" "") ======================================================================== ====File: refleks_switcher.cfr ======================================================================== The LVS run "refleks_switcher" has completed successfully. Compare problems were detected in 1 cells. 1 cells had nets mismatches. 1 cells had pins mismatches. 21 cells expanded 9 cells matched No Extraction Problems were detected. Press "OK" to enter the LVS Debug Environment. Press "Cancel" to close this Dialog box. LVS Run "refleks_switcher" is located in /media/cadence/runs/LVS/refleks_switcher_lvs