module touch_key_adc(
clk,//in
rst_n,//in
//clk_switch,//period in,	000:20ms;	001:50ms;	010:100ms;	011:200ms;	100:500ms;	default:200ms.
//power_down,//in
comp_i,//in
clk_o,
adc_en,
//channel1,
//channel2,
//channel3,
//channel4,
//channel5,
//channel6,
//channel7,
//channel8,
//channel9,
//channel10,
KG11,
KG10,
KG9,
KG8,
KG7,
KG6,
KG5,
KG4,
KG3,
KG2,
KG1,
KG0,
//KG12,
KR11,
KR10,
KR9,
KR8,
KR7,
KR6,
KR5,
KR4,
KR3,
KR2,
KR1,
KR0,
//KR12,
K1,
K2,
K3,
K4,
K5,
D11,
D10,
D9,
D8,
D7,
D6,
D5,
D4,
D3,
D2,
D1,
D0
);

//----------parameter------------
parameter	ADC_B	= 12;
parameter	COMP	= 4'ha;//10;
parameter	COMP_M	= ADC_B == 15 ? 16'h8000 :
					  ADC_B == 14 ? 15'h4000 :
					  ADC_B == 13 ? 14'h2000 :
					  ADC_B == 12 ? 13'h1000 :
					  ADC_B == 11 ? 12'h0800 :	
					  ADC_B == 10 ? 11'h0400 : 13'h1000;
//parameter	I2C_ADR	= 7'b0000111;
//
//parameter	IDLE_C	= 2'b00;
//parameter	CHANNEL	= 2'b01;
//parameter	GAP		= 2'b11;

parameter	IDLE_S	= 4'b0000;
parameter	READY	= 4'b0001;
parameter	RESET	= 4'b0011;
parameter	GAP1	= 4'b0010;
parameter	CHARGE	= 4'b0110;
parameter	GAP2	= 4'b0111;
parameter	SHARE	= 4'b0101;
parameter	GAP3	= 4'b0100;
parameter	GAP4	= 4'b1100;
parameter	CONVERT	= 4'b1101;
parameter	CALCUL	= 4'b1111;

parameter	IDLE	= 4'b0000;
parameter	SET		= 4'b0001;
parameter	DATA11	= 4'b0011;
parameter	DATA10	= 4'b0010;
parameter	DATA9	= 4'b0110;
parameter	DATA8	= 4'b0111;
parameter	DATA7	= 4'b0101;
parameter	DATA6	= 4'b0100;
parameter	DATA5	= 4'b1100;
parameter	DATA4	= 4'b1101;
parameter	DATA3	= 4'b1111;  
parameter	DATA2	= 4'b1110;
parameter	DATA1	= 4'b1010;
parameter	DATA0	= 4'b1011;
parameter	CAL_EN	= 4'b1001;
	
//-----------prot type---------------
input					clk;
input					rst_n;
//input	[2:0]			clk_switch;
//input					power_down;
input					comp_i;
output					clk_o;
output					adc_en;
//output					channel1;
//output					channel2;
//output					channel3;
//output					channel4;
//output					channel5;
//output					channel6;
//output					channel7;
//output					channel8;
//output					channel9;
//output					channel10;
output					KG0;
output					KG1;
output					KG2;
output					KG3;
output					KG4;
output					KG5;
output					KG6;
output					KG7;
output					KG8;
output					KG9;
output					KG10;
output					KG11;
//output					KG12;
output					KR0;
output					KR1;
output					KR2;
output					KR3;
output					KR4;
output					KR5;
output					KR6;
output					KR7;
output					KR8;
output					KR9;
output					KR10;
output					KR11;
//output					KR12;
output					K1;
output					K2;
output					K3;
output					K4;
output					K5;
output					D11;
output					D10;
output					D9;
output					D8;
output					D7;
output					D6;
output					D5;
output					D4;
output					D3;
output					D2;
output					D1;
output					D0;
//output					scl;
//output					sda;
                		
//reg						reg_adcen;
//reg		[1:10]			reg_channel;
//reg		[ADC_B-1:0]		reg_kg;
reg		[ADC_B-1:0]		reg_kg1;	
//reg		[ADC_B-1:0]		reg_kr;
reg		[ADC_B-1:0]		reg_kr1;
reg		[1:5]			reg_k;
//reg						reg_scl;
//reg						reg_sda;
reg						reg_clko;
reg		[11:0]			reg_data;

//----------internal reg----------
reg		[3:0]			reg_state_s;//scan
reg		[3:0]			nxt_state_s;
//reg		[1:0]			reg_state_c;//channel
//reg		[1:0]			nxt_state_c;
reg		[3:0]			reg_state;//dat
reg		[3:0]			nxt_state;
reg		[2:0]			reg_cnt;
//reg		[9:0]			reg_c;
reg		[7:0]			reg_count;
reg		[4:0]			reg_gapcnt_s;
//reg		[4:0]			reg_gapcnt_c;
reg		[1:0]			reg_rstn;
reg		[7:0]			reg_q;
//reg						reg_start;
//reg		[17:0]			reg_div;
//reg		[ADC_B+1:0]		reg_cal;
//reg		[10:1]			reg_cc;
//reg		[3:0]			reg_div_clk;
//reg						reg_clk;
//reg						reg_scl_en;
//reg						reg_dat_en;
//reg						reg_comp;
reg						reg_convert;
reg						reg_osc;
reg						reg_cal_en;
//reg						reg_end;
//reg						reg_ref;
//reg		[ADC_B-1:0]		reg_ref1;
//reg		[ADC_B-1:0]		reg_ref2;
//reg		[ADC_B-1:0]		reg_ref3;
//reg		[ADC_B-1:0]		reg_ref4;
//reg		[ADC_B-1:0]		reg_ref5;
//reg		[ADC_B-1:0]		reg_ref6;
//reg		[ADC_B-1:0]		reg_ref7;
//reg		[ADC_B-1:0]		reg_ref8;
//reg		[ADC_B-1:0]		reg_ref9;
//reg		[ADC_B-1:0]		reg_ref10;
//reg						reg_i2c;
//reg		[4:0]			reg_bit_cnt;
//reg		[1:0]			reg_len_cnt;
reg						reg_done;

//assign {channel1,channel2,channel3,channel4,channel5,channel6,channel7,channel8,channel9,channel10}	= reg_channel;
assign {KG11,KG10,KG9,KG8,KG7,KG6,KG5,KG4,KG3,KG2,KG1,KG0}	= (reg_state_s==RESET)?{12'hfff}:reg_kg1;//reg_kg|
assign {KR11,KR10,KR9,KR8,KR7,KR6,KR5,KR4,KR3,KR2,KR1,KR0}	= reg_kr1;//reg_kr&
assign {K1,K2,K3,K4,K5}	= reg_k;
assign adc_en	= 1'b1;//reg_adcen;
assign clk_o	= reg_clko;
assign {D11,D10,D9,D8,D7,D6,D5,D4,D3,D2,D1,D0} = reg_data;
//----------------syn-----------
always @ (posedge clk)
begin   
	reg_rstn <= {reg_rstn[0],rst_n};
end     
        
always @ (posedge clk or negedge reg_rstn[1])
begin   
	if(!reg_rstn[1])		reg_q <= 8'h00;
	else if(reg_q != 8'h80)	reg_q <= reg_q +8'h01;
end     

wire	wire_rstn;
assign	wire_rstn = reg_q[7];

////---------------clk-----------
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn) reg_div_clk <= 4'h0;
//	else reg_div_clk <= reg_div_clk + 4'h1;
//end
//
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)			reg_clk <= 1'b0;
//	else if(&reg_div_clk)	reg_clk <= ~reg_clk;
//end
//
////------------scl-----------
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_scl <= 1'b1;
//	else if(reg_scl_en) begin// & (!reg_err)
//		if(&{reg_clk,reg_div_clk})
//			reg_scl <= ~reg_scl;
//	end
//	else 	reg_scl <= 1'b1;
//end
//
////---------------period-------------
//always @(posedge reg_clk or negedge wire_rstn)
//begin
//	if(!wire_rstn) reg_div <= 18'h0_0000;
//	else begin
//		case(clk_switch)
//		3'b000:begin//period 20ms
//			if(reg_div == 18'h0_270F) reg_div <= 18'h0_0000;//9999
//			else reg_div <= reg_div + 18'h0_0001;
//		end
//		3'b001:begin//period 50ms
//			if(reg_div == 18'h0_61A7) reg_div <= 18'h0_0000;//24999
//			else reg_div <= reg_div + 18'h0_0001;
//		end
//		3'b010:begin//period 100ms
//			if(reg_div == 18'h0_C34F) reg_div <= 18'h0_0000;//49999
//			else reg_div <= reg_div + 18'h0_0001;
//		end
//		3'b011:begin//period 200ms
//			if(reg_div == 18'h1_869F) reg_div <= 18'h0_0000;//99999
//			else reg_div <= reg_div + 18'h0_0001;
//		end
//		3'b100:begin//period 500ms
//			if(reg_div == 18'h3_D08F) reg_div <= 18'h0_0000;//249999
//			else reg_div <= reg_div + 18'h0_0001;
//		end
//		default:begin//period 200ms
//			if(reg_div == 18'h1_869F) reg_div <= 18'h0_0000;//99999
//			else reg_div <= reg_div + 18'h0_0001;
//		end
//		endcase
//	end
//end
//
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)		reg_start <= 1'b0;
//	else if(~|reg_div)	reg_start <= 1'b1;
//	else if(reg_start)	reg_start <= 1'b0;
//end

//------------------FSM-----------------
//FSM 1
//always @(reg_state_c or reg_start or power_down or reg_gapcnt_c or reg_done or reg_cnt or reg_c)
//begin
//	nxt_state_c = 2'b00;
//	case(reg_state_c)
//		IDLE_C:	if(reg_start && !power_down)nxt_state_c = CHANNEL;
//				else						nxt_state_c = IDLE_C;
//		CHANNEL:if(reg_cnt[2] && reg_done)	nxt_state_c = GAP;								
//				else						nxt_state_c = CHANNEL;
//		GAP:	if(reg_c[9] && (&reg_gapcnt_c))
//											nxt_state_c = IDLE_C;
//				else if(&reg_gapcnt_c)		nxt_state_c = CHANNEL;
//				else						nxt_state_c = GAP;
//		default:							nxt_state_c = IDLE_C; 
//	endcase
//end
//
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_state_c <= 2'b00;
//	else			reg_state_c <= nxt_state_c;
//end
//
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_gapcnt_c <= 5'h00;
//	else begin
//		case(nxt_state_c)
//			IDLE_C:	reg_gapcnt_c <= 5'h00;
//			CHANNEL:reg_gapcnt_c <= 5'h00;
//			GAP:	reg_gapcnt_c <= reg_gapcnt_c + 5'h01; 
//		endcase
//	end
//end
//
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_c <= 10'h000;
//	else begin
//		case(nxt_state_c)
//			IDLE_C:					reg_c <= 10'h200;
//			GAP: if(~|reg_gapcnt_c)	reg_c <= {reg_c[0],reg_c[9:1]}; 
//		endcase
//	end
//end
//
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_channel <= 10'h000;
//	else begin
//		case(nxt_state_c)
//			IDLE_C:	reg_channel <= 10'h000;
//			CHANNEL:reg_channel <= reg_c;
//			GAP:	reg_channel <= 10'h000; 
//		endcase
//	end
//end
//FSM 2
always @(reg_state_s or reg_gapcnt_s or reg_cnt  or reg_count or reg_k[4] or reg_done)//or reg_channel
begin
	nxt_state_s = 4'h0;
	case(reg_state_s)
		IDLE_S: nxt_state_s = READY;
//		READY:	if(|reg_channel) nxt_state_s = RESET;
//				else			 nxt_state_s = READY;
		READY:	nxt_state_s = RESET;
		RESET:	if(reg_count[7]) nxt_state_s = GAP1;//&& (~|reg_count[6:0])				 
				else			 nxt_state_s = RESET;
		GAP1:	if(&reg_gapcnt_s)nxt_state_s = CHARGE;
				else			 nxt_state_s = GAP1;
		CHARGE:	if(&reg_count)	 nxt_state_s = GAP2;
				else			 nxt_state_s = CHARGE;
		GAP2:	if(&reg_gapcnt_s)nxt_state_s = SHARE;
				else			 nxt_state_s = GAP2;
		SHARE:	if(&reg_count)	 nxt_state_s = GAP3;
				else			 nxt_state_s = SHARE;
		GAP3:	if(&reg_gapcnt_s)nxt_state_s = GAP4;
				else			 nxt_state_s = GAP3;
		GAP4:	if(&reg_gapcnt_s && !reg_k[4])
								 nxt_state_s = CONVERT;
				else			 nxt_state_s = GAP4;
		CONVERT:if(reg_done && reg_cnt[2])
								 nxt_state_s = IDLE_S;
				else if(reg_done)nxt_state_s = RESET;
				else			 nxt_state_s = CONVERT;
//		CONVERT:if(&reg_count)	 nxt_state_s = CALCUL;
//				else			 nxt_state_s = CONVERT;
//		CALCUL: if(reg_cnt[2] && (&reg_gapcnt_s))
//						 		 nxt_state_s = IDLE_S;
//		else if(&reg_gapcnt_s)	 nxt_state_s = RESET;
//		else					 nxt_state_s = CALCUL;
	endcase
end

always @(posedge clk or negedge wire_rstn)
begin
	if(!wire_rstn)	reg_state_s <= 4'h0;
	else			reg_state_s <= nxt_state_s;
end


always @(posedge clk or negedge wire_rstn)
begin
	if(!wire_rstn)	reg_count <= 8'h00;
	else begin
		case(nxt_state_s)
			IDLE_S: reg_count <= 8'h00;
			READY:	reg_count <= 8'h00;
			RESET:	reg_count <= reg_count + 8'h01;
			GAP1:	reg_count <= 8'h00;
			CHARGE:	reg_count <= reg_count + 8'h01;
			GAP2:	reg_count <= 8'h00;
			SHARE:	reg_count <= reg_count + 8'h01;
			GAP3:	reg_count <= 8'h00;
//			CONVERT:reg_count <= reg_count + 8'h01;
//			CALCUL: reg_count <= 8'h00;
		endcase
	end
end

always @(posedge clk or negedge wire_rstn)
begin
	if(!wire_rstn)	reg_gapcnt_s <= 5'h00;
	else begin
		case(nxt_state_s)
			IDLE_S: reg_gapcnt_s <= 5'h00;
			RESET:	reg_gapcnt_s <= 5'h00;
			GAP1:	reg_gapcnt_s <= reg_gapcnt_s + 5'h01;
			CHARGE:	reg_gapcnt_s <= 5'h00;
			GAP2:	reg_gapcnt_s <= reg_gapcnt_s + 5'h01;
			SHARE:	reg_gapcnt_s <= 5'h00;
			GAP3:	reg_gapcnt_s <= reg_gapcnt_s + 5'h01;
			GAP4:	reg_gapcnt_s <= reg_gapcnt_s + 5'h01;
			CONVERT:reg_gapcnt_s <= 5'h00;
//			CALCUL:	reg_gapcnt_s <= reg_gapcnt_s + 5'h01;
		endcase
	end
end

always @(posedge clk or negedge wire_rstn)
begin
	if(!wire_rstn)	reg_cnt <= 3'b000;
	else begin
		case(nxt_state_s)
			IDLE_S:						reg_cnt <= 3'b000;
			CONVERT:if(&reg_gapcnt_s)	reg_cnt <= reg_cnt + 3'h1;
//			CALCUL:if(&reg_count)	reg_cnt <= reg_cnt + 3'h1;
		endcase
	end
end
//FSM 3
always @(reg_state or reg_convert)
begin
	nxt_state = 4'h0;
	case(reg_state)
		IDLE:if(reg_convert)	
				nxt_state = SET;
		SET:	nxt_state = DATA11;			
		DATA11:	nxt_state = DATA10;
		DATA10:	nxt_state = DATA9;
		DATA9:	nxt_state = DATA8;
		DATA8:	nxt_state = DATA7;
		DATA7:	nxt_state = DATA6;
		DATA6:	nxt_state = DATA5;
		DATA5:	nxt_state = DATA4;
		DATA4:	nxt_state = DATA3;
		DATA3:	nxt_state = DATA2;
		DATA2:	nxt_state = DATA1;		
		DATA1:	nxt_state = DATA0;
		DATA0:	nxt_state = CAL_EN;
		CAL_EN:	nxt_state = IDLE;
	endcase    
end

always @(negedge reg_clko or negedge wire_rstn)
begin
	if(!wire_rstn)	reg_state <= 4'h0;
	else			reg_state <= nxt_state;
end

//-----------------connect to ADC---------------
//FSM 1
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_adcen <= 1'b0;
//	else begin
//		case(nxt_state_c)
//			IDLE_C: reg_adcen <= 1'b0;
//			CHANNEL:reg_adcen <= 1'b1;
//		endcase
//	end
//end
//FSM 2
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_kg <= 13'h0000;
//	else begin
//		case(nxt_state_s)
//			IDLE_S:	reg_kg <= 13'h0000;
//			RESET:	reg_kg <= 13'h1fff;
//			GAP1:	reg_kg <= 13'h0000;
////			CALCUL:	reg_kg <= 13'h0000;
//		endcase
//	end
//end

//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_kr <= 13'h0000;
//	else begin
//		case(nxt_state_s)
//			IDLE_S:	reg_kr <= 13'h0000;
//			RESET:	reg_kr <= 13'h0000;
//			CONVERT:reg_kr <= 13'h1fff;
////			CALCUL:	reg_kr <= 13'h0000;
//		endcase
//	end
//end

always @(posedge clk or negedge wire_rstn)
begin
	if(!wire_rstn)	reg_k[1] <= 1'b0;
	else begin
		case(nxt_state_s)
			RESET:	reg_k[1] <= 1'b0;
			CHARGE:	reg_k[1] <= 1'b1;
			GAP2:	reg_k[1] <= 1'b0;
		endcase
	end
end

always @(posedge clk or negedge wire_rstn)
begin
	if(!wire_rstn)	reg_k[2] <= 1'b0;
	else begin
		case(nxt_state_s)
			IDLE_S:	reg_k[2] <= 1'b0;
			RESET:	reg_k[2] <= 1'b1;
			GAP1:	reg_k[2] <= 1'b0;
		endcase
	end
end

always @(posedge clk or negedge wire_rstn)
begin
	if(!wire_rstn)	reg_k[3] <= 1'b0;
	else begin
		case(nxt_state_s)
			RESET:	reg_k[3] <= 1'b0;
			SHARE:	reg_k[3] <= 1'b1;
			GAP3:	reg_k[3] <= 1'b0;
		endcase
	end
end

always @(posedge clk or negedge wire_rstn)
begin
	if(!wire_rstn)	reg_k[4] <= 1'b0;
	else begin
		case(nxt_state_s)
			IDLE_S:	reg_k[4] <= 1'b0;
			RESET:	reg_k[4] <= 1'b1;
			GAP4:	reg_k[4] <= 1'b0;
		endcase
	end
end

always @(posedge clk or negedge wire_rstn)
begin
	if(!wire_rstn)	reg_k[5] <= 1'b0;
	else begin
		case(nxt_state_s)
			IDLE_S: reg_k[5] <= 1'b0;
			RESET:	reg_k[5] <= 1'b1;
		endcase
	end
end

always @(posedge clk or negedge wire_rstn)
begin
	if(!wire_rstn)					reg_convert <= 1'b0;
	else if(reg_convert)			reg_convert <= 1'b0;
	else if( (nxt_state_s==CONVERT) && (&reg_gapcnt_s) )
									reg_convert <= 1'b1;
end

always @(posedge clk or negedge wire_rstn)
begin
	if(!wire_rstn)			reg_osc <= 1'b0;
	else if(reg_convert)	reg_osc <= 1'b1;
	else if(reg_done)		reg_osc <= 1'b0;
end

always @(posedge clk or negedge wire_rstn)
begin
	if(!wire_rstn)		reg_clko <= 1'b0;
	else if(reg_convert)reg_clko <= 1'b0;
	else if(reg_osc)	reg_clko <= ~reg_clko;
	else				reg_clko <= 1'b1;
end
//FSM 3
always @(negedge reg_clko or negedge wire_rstn)
begin
	if(!wire_rstn)	reg_kr1			<= 12'h000;
	else begin
		case(nxt_state)
			IDLE:	reg_kr1			<= 12'h000;
			SET:	reg_kr1[11]		<= 1'b1;			
			DATA11:	reg_kr1[11:10]	<= {comp_i,1'b1};
			DATA10:	reg_kr1[10:9]	<= {comp_i,1'b1};
			DATA9:	reg_kr1[9:8]	<= {comp_i,1'b1};
			DATA8:	reg_kr1[8:7]	<= {comp_i,1'b1};
			DATA7:	reg_kr1[7:6]	<= {comp_i,1'b1};
			DATA6:	reg_kr1[6:5]	<= {comp_i,1'b1};
			DATA5:	reg_kr1[5:4]	<= {comp_i,1'b1};
			DATA4:	reg_kr1[4:3]	<= {comp_i,1'b1};
			DATA3:	reg_kr1[3:2]	<= {comp_i,1'b1};
			DATA2:	reg_kr1[2:1]	<= {comp_i,1'b1};	
			DATA1:	reg_kr1[1:0]	<= {comp_i,1'b1};
			DATA0:	reg_kr1[0]		<= comp_i;
		endcase    
	end
end

always @(negedge reg_clko or negedge wire_rstn)
begin
	if(!wire_rstn)	reg_kg1			<= 12'h000;
	else begin                  	
		case(nxt_state)         	
			IDLE:	reg_kg1			<= 12'h000;
			SET:	reg_kg1			<= {1'b0,11'h7ff};			
			DATA11:	reg_kg1[11:10]	<= {~comp_i,1'b0};
			DATA10:	reg_kg1[10:9]	<= {~comp_i,1'b0};
			DATA9:	reg_kg1[9:8]	<= {~comp_i,1'b0};
			DATA8:	reg_kg1[8:7]	<= {~comp_i,1'b0};
			DATA7:	reg_kg1[7:6]	<= {~comp_i,1'b0};
			DATA6:	reg_kg1[6:5]	<= {~comp_i,1'b0};
			DATA5:	reg_kg1[5:4]	<= {~comp_i,1'b0};
			DATA4:	reg_kg1[4:3]	<= {~comp_i,1'b0};
			DATA3:	reg_kg1[3:2]	<= {~comp_i,1'b0};
			DATA2:	reg_kg1[2:1]	<= {~comp_i,1'b0};	
			DATA1:	reg_kg1[1:0]	<= {~comp_i,1'b0};
			DATA0:	reg_kg1[0]		<= ~comp_i;
		endcase    
	end
end

always @(negedge reg_clko or negedge wire_rstn)
begin
	if(!wire_rstn)	reg_cal_en <= 1'b0;
	else begin
		case(nxt_state)
			IDLE:	reg_cal_en <= 1'b0;
			CAL_EN:	reg_cal_en <= 1'b1;
		endcase    
	end
end
//-----------------------connect to MCU------------------------
//assign sda	= reg_sda?1'bz:1'b0;
//assign scl	= reg_scl?1'bz:1'b0;
//
//always @(posedge reg_clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)											reg_scl_en <= 1'b0;
//	else if(~|{reg_i2c,reg_adcen} || (nxt_state_s==RESET))	reg_scl_en <= 1'b0;
//	else if( (nxt_state_c==GAP) && reg_c[9] && reg_ref)		reg_scl_en <= 1'b1;
//end

always @(posedge clk or negedge wire_rstn)
begin
	if(!wire_rstn)		reg_done <= 1'b0;
	else if(reg_done)	reg_done <= 1'b0;
	else if(reg_cal_en)	reg_done <= 1'b1;
end

//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)					reg_cal <= 'h0;
//	else if(nxt_state_s==IDLE_S)	reg_cal <= 'h0;
//	else if(reg_cal_en && !reg_done)reg_cal <= reg_cal + {2'b00,reg_kr1};
//end

//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)								reg_comp <= 1'b0;
//	else if(reg_comp)							reg_comp <= 1'b0;
//	else if(reg_cal_en && reg_cnt[2] && reg_ref)reg_comp <= 1'b1;
//end

//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)														reg_cc[1] <= 1'b0;
//	else if(reg_comp && reg_channel[1]) begin
//		if( ({1'b1,reg_cal[ADC_B+1:2]}-{1'b0,reg_ref1})>(COMP+COMP_M) )	reg_cc[1] <= 1'b1;
//	end
//	else if(~|{reg_i2c,reg_adcen} || (reg_i2c&&(nxt_state_s==RESET)))	reg_cc[1] <= 1'b0;
//end
//
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)														reg_cc[2] <= 1'b0;
//	else if(reg_comp && reg_channel[2]) begin
//		if( ({1'b1,reg_cal[ADC_B+1:2]}-{1'b0,reg_ref2})>(COMP+COMP_M) )	reg_cc[2] <= 1'b1;
//	end
//	else if(~|{reg_i2c,reg_adcen} || (reg_i2c&&(nxt_state_s==RESET)))	reg_cc[2] <= 1'b0;
//end
//
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)														reg_cc[3] <= 1'b0;
//	else if(reg_comp && reg_channel[3]) begin
//		if( ({1'b1,reg_cal[ADC_B+1:2]}-{1'b0,reg_ref3})>(COMP+COMP_M) )	reg_cc[3] <= 1'b1;
//	end
//	else if(~|{reg_i2c,reg_adcen} || (reg_i2c&&(nxt_state_s==RESET)))	reg_cc[3] <= 1'b0;
//end
//
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)														reg_cc[4] <= 1'b0;
//	else if(reg_comp && reg_channel[4]) begin
//		if( ({1'b1,reg_cal[ADC_B+1:2]}-{1'b0,reg_ref4})>(COMP+COMP_M) )	reg_cc[4] <= 1'b1;
//	end
//	else if(~|{reg_i2c,reg_adcen} || (reg_i2c&&(nxt_state_s==RESET)))	reg_cc[4] <= 1'b0;
//end
//
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)														reg_cc[5] <= 1'b0;
//	else if(reg_comp && reg_channel[5]) begin
//		if( ({1'b1,reg_cal[ADC_B+1:2]}-{1'b0,reg_ref5})>(COMP+COMP_M) )	reg_cc[5] <= 1'b1;
//	end
//	else if(~|{reg_i2c,reg_adcen} || (reg_i2c&&(nxt_state_s==RESET)))	reg_cc[5] <= 1'b0;
//end
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)														reg_cc[6] <= 1'b0;
//	else if(reg_comp && reg_channel[6]) begin
//		if( ({1'b1,reg_cal[ADC_B+1:2]}-{1'b0,reg_ref6})>(COMP+COMP_M) )	reg_cc[6] <= 1'b1;
//	end
//	else if(~|{reg_i2c,reg_adcen} || (reg_i2c&&(nxt_state_s==RESET)))	reg_cc[6] <= 1'b0;
//end
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)														reg_cc[7] <= 1'b0;
//	else if(reg_comp && reg_channel[7]) begin
//		if( ({1'b1,reg_cal[ADC_B+1:2]}-{1'b0,reg_ref7})>(COMP+COMP_M) )	reg_cc[7] <= 1'b1;
//	end
//	else if(~|{reg_i2c,reg_adcen} || (reg_i2c&&(nxt_state_s==RESET)))	reg_cc[7] <= 1'b0;
//end
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)														reg_cc[8] <= 1'b0;
//	else if(reg_comp && reg_channel[8]) begin
//		if( ({1'b1,reg_cal[ADC_B+1:2]}-{1'b0,reg_ref8})>(COMP+COMP_M) )	reg_cc[8] <= 1'b1;
//	end
//	else if(~|{reg_i2c,reg_adcen} || (reg_i2c&&(nxt_state_s==RESET)))	reg_cc[8] <= 1'b0;
//end
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)														reg_cc[9] <= 1'b0;
//	else if(reg_comp && reg_channel[9]) begin
//		if( ({1'b1,reg_cal[ADC_B+1:2]}-{1'b0,reg_ref9})>(COMP+COMP_M) )	reg_cc[9] <= 1'b1;
//	end
//	else if(~|{reg_i2c,reg_adcen} || (reg_i2c&&(nxt_state_s==RESET)))	reg_cc[9] <= 1'b0;
//end
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)														reg_cc[10] <= 1'b0;
//	else if(reg_comp && reg_channel[10]) begin
//		if( ({1'b1,reg_cal[ADC_B+1:2]}-{1'b0,reg_ref10})>(COMP+COMP_M) )reg_cc[10] <= 1'b1;
//	end
//	else if(~|{reg_i2c,reg_adcen} || (reg_i2c&&(nxt_state_s==RESET)))	reg_cc[10] <= 1'b0;
//end
//
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)				reg_i2c <= 1'b0;
//	else if(nxt_state_s==RESET)	reg_i2c <= 1'b0;//or
//	else if(reg_scl_en)			reg_i2c <= 1'b1;
//end

////------------------------ref-----------------
//always @(negedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)						reg_ref <= 1'b0;
//	else if(power_down)					reg_ref <= 1'b0;
//	else if(reg_c[9] && (&reg_gapcnt_c))reg_ref <= 1'b1;
//end
//
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_ref1 <= 12'h000;
//	else if(reg_done && reg_cnt[2] && !reg_ref && reg_channel[1]) begin
//		reg_ref1 <= reg_cal[ADC_B+1:2];
//	end
//end
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_ref2 <= 12'h000;
//	else if(reg_done && reg_cnt[2] && !reg_ref && reg_channel[2]) begin
//		reg_ref2 <= reg_cal[ADC_B+1:2];
//	end
//end	
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_ref3 <= 12'h000;
//	else if(reg_done && reg_cnt[2] && !reg_ref && reg_channel[3]) begin
//		reg_ref3 <= reg_cal[ADC_B+1:2];
//	end
//end	
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_ref4 <= 12'h000;
//	else if(reg_done && reg_cnt[2] && !reg_ref && reg_channel[4]) begin
//		reg_ref4 <= reg_cal[ADC_B+1:2];
//	end
//end	
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_ref5 <= 12'h000;
//	else if(reg_done && reg_cnt[2] && !reg_ref && reg_channel[5]) begin
//		reg_ref5 <= reg_cal[ADC_B+1:2];
//	end
//end	
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_ref6 <= 12'h000;
//	else if(reg_done && reg_cnt[2] && !reg_ref && reg_channel[6]) begin
//		reg_ref6 <= reg_cal[ADC_B+1:2];
//	end
//end
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_ref7 <= 12'h000;
//	else if(reg_done && reg_cnt[2] && !reg_ref && reg_channel[7]) begin
//		reg_ref7 <= reg_cal[ADC_B+1:2];
//	end
//end
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_ref8 <= 12'h000;
//	else if(reg_done && reg_cnt[2] && !reg_ref && reg_channel[8]) begin
//		reg_ref8 <= reg_cal[ADC_B+1:2];
//	end
//end	
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_ref9 <= 12'h000;
//	else if(reg_done && reg_cnt[2] && !reg_ref && reg_channel[9]) begin
//		reg_ref9 <= reg_cal[ADC_B+1:2];
//	end
//end
//always @(posedge clk or negedge wire_rstn)
//begin
//	if(!wire_rstn)	reg_ref10 <= 12'h000;
//	else if(reg_done && reg_cnt[2] && !reg_ref && reg_channel[10]) begin
//		reg_ref10 <= reg_cal[ADC_B+1:2];
//	end
//end				
//
////test//
always @(posedge clk or negedge wire_rstn)
begin
	if(!wire_rstn)		reg_data <= 12'h000;
	else if(reg_done)	reg_data <= reg_kr1;
end
//output	[9:0]	test_c;
//assign	test_c = reg_cc;
////test//
endmodule