library ieee;
use ieee.std_logic_1164.all;

library analogdevice_lib;
use analogdevice_lib.all;

library st_lib;
use st_lib.all;

architecture archi of systeme_comparateur is

component analog_ADG704

	generic (INPUTS_SEL: integer);
	
	port(EN : in std_logic;
	     A  : in std_logic_vector (INPUTS_SEL-1 downto 0);
	     S  : in real_vector (2**INPUTS_SEL-1 downto 0);
	     D  : out real);
	     
end component;

--component mux4to1

--	port(En: in std_logic;
--	     A0: in std_logic;
--	     A1: in std_logic;
--	     S1: in real;
--	     S2: in real;
--	     S3: in real;
--	     S4: in real;
--	     D : out real);
	     
--end component;

--component mux8to1

--	port(En: in std_logic;
--	     A0: in std_logic;
--	     A1: in std_logic;
--	     A2: in std_logic;
--	     S1: in real;
--	     S2: in real;
--	     S3: in real;
--	     S4: in real;
--	     S5: in real;
--	     S6: in real;
--	     S7: in real;
--	     S8: in real;
--	     D : out real);
	     
--end component;

component analog_ADG708

	generic (INPUTS_SEL: integer);
	
	port(EN : in std_logic;
	     A  : in std_logic_vector (INPUTS_SEL-1 downto 0);
	     S  : in real_vector (2**INPUTS_SEL-1 downto 0);
	     D  : out real);
	     
end component;

component analog_comparateur

	generic (vcc   : real;
		 gnd   : real);  

	port(in_pos : in real;
	     in_neg : in real;
             s_comp : out real); 	

end component;

component analog_mux_2to1

	port(A     : in std_logic;
	     S1,S2 : in real;
	     D     : out real);
	     
end component;

component sinus_generator

	generic(AMP: real;
		FREQ: real);
	
	port(sinus: out real);
	
end component;

signal mux1_mux5, mux5_comp1, mux2_comp1, mux3_out, mux4_comp2 : real;

signal int1, int2, int3, int4, int5, int6, int7, int8,
       int9, int10, int11, int12, int13, int14, int15, int16,
       int17, int18, int19, int20, int21, int22, int23, int24 : real;
             
begin

	u1: sinus_generator 	
	
		generic map (AMP => 0.5, FREQ => 20000000.0)

		port map (int1);
	
	u2: sinus_generator 	
	
		generic map (AMP => 1.5, FREQ => 20000000.0)

		port map (int2);
	
	u3: sinus_generator 	
	
		generic map (AMP => 1.3, FREQ => 20000000.0)

		port map (int3);
	
	u4: sinus_generator 	
	
		generic map (AMP => 1.4, FREQ => 20000000.0)

		port map (int4);
	
	u5: sinus_generator 	
	
		generic map (AMP => 2.2, FREQ => 20000000.0)

		port map (int5);
	
	u6: sinus_generator 	
	
		generic map (AMP => 4.8, FREQ => 20000000.0)

		port map (int6);
	
	u7: sinus_generator 	
	
		generic map (AMP => 1.9, FREQ => 20000000.0)

		port map (int7);
	
	u8: sinus_generator 	
	
		generic map (AMP => 3.6, FREQ => 20000000.0)

		port map (int8);
	
	u9: sinus_generator 	
	
		generic map (AMP => 4.1, FREQ => 20000000.0)

		port map (int9);
	
	u10: sinus_generator 	
	
		generic map (AMP => 2.2, FREQ => 20000000.0)

		port map (int10);
	
	u11: sinus_generator 	
	
		generic map (AMP => 2.6, FREQ => 20000000.0)

		port map (int11);
	
	u12: sinus_generator 	
	
		generic map (AMP => 0.8, FREQ => 20000000.0)

		port map (int12);
	
	u13: sinus_generator 	
	
		generic map (AMP => 3.3, FREQ => 20000000.0)

		port map (int13);
	
	u14: sinus_generator 	
	
		generic map (AMP => 5.0, FREQ => 20000000.0)

		port map (int14);
	
	u15: sinus_generator 	
	
		generic map (AMP => 4.0, FREQ => 20000000.0)

		port map (int15);
	
	u16: sinus_generator 	
	
		generic map (AMP => 4.9, FREQ => 20000000.0)

		port map (int16);
	
	u17: sinus_generator 	
	
		generic map (AMP => 1.1, FREQ => 20000000.0)

		port map (int17);
	
	u18: sinus_generator 	
	
		generic map (AMP => 3.7, FREQ => 20000000.0)

		port map (int18);
	
	u19: sinus_generator 	
	
		generic map (AMP => 0.9, FREQ => 20000000.0)

		port map (int19);
	
	u20: sinus_generator 	
	
		generic map (AMP => 3.1, FREQ => 20000000.0)

		port map (int20);
	
	u21: sinus_generator
	
	 	generic map (AMP => 4.4, FREQ => 20000000.0)

		port map (int21);
	
	u22: sinus_generator 	
	
		generic map (AMP => 0.5, FREQ => 20000000.0)

		port map (int22);
	
	u23: sinus_generator
	
	 	generic map (AMP => 4.8, FREQ => 20000000.0)

		port map (int23);
	
	u24: sinus_generator
	
	 	generic map (AMP => 3.8, FREQ => 20000000.0)

		port map (int24);
	
	mux1: analog_ADG704	
	
		generic map (INPUTS_SEL => 2)
	
		port map (En => enable_mux1,
			  A => A_mux1,
			  S_mux1(0) => int1,
			  S_mux1(1) => int2,
			  S_mux1(2) => int3,
			  S_mux1(3) => int4,
			  D => mux1_mux5);

--	mux1: mux4to1
	
--		port map(enable_mux1,
--			 A0_mux1,
--			 A1_mux1,
--			 int1,
--			 int2,
--			 int3,
--			 int4,
--			 mux1_mux5);
			 		
	mux2: analog_ADG708	
	
		generic map (INPUTS_SEL => 3)
			
		port map (En => enable_mux2,
			  A => A_mux2,
			  S_mux2(0) => int5,
			  S_mux2(1) => int6,
			  S_mux2(2) => int7,
			  S_mux2(3) => int8,
			  S_mux2(4) => int9,
			  S_mux2(5) => int10,
			  S_mux2(6) => int11,
			  S_mux2(7) => int12,
			  D => mux2_comp1);

--	mux2: mux8to1
	
--		port map(enable_mux2,
--			 A0_mux2,
--			 A1_mux2,
--			 A2_mux2,
--			 int5,
--			 int6,
--			 int7,
--			 int8,
--			 int9,
--			 int10,
--			 int11,
--			 int12,
--			 mux2_comp1);
			 			
	cmp1: analog_comparateur
	
		generic map (vcc => 5.0, gnd => 0.0)
		
		port map (mux1_mux5, mux2_comp1, Sortie_comp1);

	mux3: analog_ADG704
	
		generic map (INPUTS_SEL => 2)
	
		port map (En => enable_mux3,
			  A => A_mux3,
			  S_mux3(0) => int13,
			  S_mux3(1) => int14,
			  S_mux3(2) => int15,
			  S_mux3(3) => int16,
			  D => mux3_out);
			
--	mux3: mux4to1
	
--	port map(enable_mux3,
--		 A0_mux3,
--		 A1_mux3,
--		 int13,
--		 int14,
--		 int15,
--		 int16,
--		 mux3_out);
			 		
	mux4: analog_ADG708
	
		generic map (INPUTS_SEL => 3)
		
		port map (En => enable_mux4,
			  A => A_mux4,
			  S_mux4(0) => int17,
			  S_mux4(1) => int18,
			  S_mux4(2) => int19,
			  S_mux4(3) => int20,
			  S_mux4(4) => int21,
			  S_mux4(5) => int22,
			  S_mux4(6) => int23,
			  S_mux4(7) => int24,
			  D => mux4_comp2);

--	mux4: mux8to1
	
--		port map(enable_mux4,
--			 A0_mux4,
--			 A1_mux4,
--			 A2_mux4,
--			 int17,
--			 int18,
--			 int19,
--			 int20,
--			 int21,
--			 int22,
--			 int23,
--			 int24,
--			 mux4_comp2);
			 			
	comp2: analog_comparateur
	
		generic map (vcc => 5.0, gnd => 0.0)
		
		port map (mux3_out, mux4_comp2, Sortie_comp2);
			
	mux5: analog_mux_2to1
					
		port map (In_switch, mux1_mux5, mux3_out, mux5_comp1);
			
end archi;