// VerilogA for Testing, DNLpart, veriloga `include "constants.vams" `include "disciplines.vams" //enSYS@gmx.com module DNLpart (vclk,vin,d0,d1,d2,d3,d4,d5,d6,d7); input d0,d1,d2,d3,d4,d5,d6,d7; input vclk,vin; electrical d0,d1,d2,d3,d4,d5,d6,d7; electrical vin,vclk; parameter real vtrans_clk = 0.5; // Threshold parameter real fullscale = 1.0; // For Gain Error Estimation parameter integer maxcode = 128; // Number of bins parameter integer method = 0; real X[7:0]; real Y[7:0]; real dnl[7:0]; real inl[7:0]; integer maxcount,count,i; real measbin,offseterr,gainerr,dnlmax,dnlmin,inlmax,inlmin; integer dnlout,inlout; real S,S1,S2,S3,S4,P,P1,P0,A1,A0; analog begin @(initial_step) begin for(i=0;i<1023;i=i+1)begin X[i] = 0; Y[i] = 0; dnl[i] = 0; inl[i] = 0; end count = 0; dnlout = $fopen("~/dnlmeasure.dat"); inlout = $fopen("~/inlmeasure.dat"); end @(cross(V(vclk) - vtrans_clk, 0))begin X[count] = $abstime; Y[count] = V(vin); count = count + 1; end @(final_step)begin maxcount = count; // Linear Approximation (Best Fit) S1 = 0; S2 = 0; S3 = 0; S4 = 0; for (i=0;idnlmax) dnlmax = dnl[i]; if (dnl[i]inlmax) inlmax = inl[i]; if (inl[i]