library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity analog_ADG708 is

	generic (INPUTS_SEL: integer);
	
	port(EN : in std_logic;
	     A  : in std_logic_vector (INPUTS_SEL-1 downto 0);
	     S  : in real_vector (2**INPUTS_SEL-1 downto 0);
	     D  : out real);
	     
end analog_ADG708;

architecture archi of analog_ADG708 is

component analog_mux_nto1
	
	generic (INPUTS_SEL : integer);
	
	port(EN : in std_logic;
	     A  : in std_logic_vector (INPUTS_SEL-1 downto 0);
	     S  : in real_vector (2**INPUTS_SEL-1 downto 0);
	     D  : out real);
end component;

begin

inst: analog_mux_nto1

	generic map (INPUTS_SEL => 3)

	port map (EN => EN,
        	  A => A,
	  	  S => S,
	  	  D => D);
		    
end archi;
