library ieee;
use ieee.std_logic_1164.all;

entity analog_comparateur is

	generic (vcc   : real;
		 gnd   : real);  

	port(in_pos : in real;
	     in_neg : in real;
             s_comp : out real); 	

end analog_comparateur;

architecture archi of analog_comparateur is
begin

	process (in_pos, in_neg)
	begin
	
		if in_pos > in_neg then
			
			s_comp <= vcc;
		
		else
		
			s_comp <= gnd;
				
		end if;
		
	end process;
	
end archi;
