library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity analog_mux_nto1 is

	generic (INPUTS_SEL: integer);
	
	port(EN : in std_logic;
	     A  : in std_logic_vector (INPUTS_SEL-1 downto 0);
	     S  : in real_vector (2**INPUTS_SEL-1 downto 0);
	     D  : out real);
	     
end analog_mux_nto1;

architecture archi of analog_mux_nto1 is

signal sel: std_logic_vector (INPUTS_SEL-1 downto 0);

begin

	sel <= A;

	D <= 0.0 when (EN = '0') else S(to_integer(unsigned(sel)));
	
end archi;
