library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity analog_mux_2to1 is

	port(A     : in std_logic;
	     S1,S2 : in real;
	     D     : out real);
	     
end analog_mux_2to1;

architecture archi of analog_mux_2to1 is
begin

	D <= S1 when A='0' else S2;	
			    
end archi;
