Warning from spectre during circuit read-in.
    WARNING (SFE-2654): VerilogA module `respoly_va' override primitive/(verilogA module) `respoly_va'.
    WARNING (SFE-2654): VerilogA module `respoly_va' override primitive/(verilogA module) `respoly_va'.
Warning from spectre during hierarchy flattening.
    WARNING (SFE-1131): Duplicate scope option `tnom' with scope `TopCircuit'. (using last value specified).

Time for Elaboration: CPU = 26.997 ms, elapsed = 28.7302 ms.
Time accumulated: CPU = 271.958 ms, elapsed = 403.317 ms.
Peak resident memory used = 51.7 Mbytes.

Time for EDB Visiting: CPU = 999 us, elapsed = 718.832 us.
Time accumulated: CPU = 272.957 ms, elapsed = 404.256 ms.
Peak resident memory used = 52.1 Mbytes.


Notice from spectre during topology check.
    No DC path from node `net013' to ground, Gmin installed to provide path.
    No DC path from node `net06' to ground, Gmin installed to provide path.
    No DC path from node `net018' to ground, Gmin installed to provide path.
        V0:p (from net018 to net017)
    No DC path from node `net013' to ground, Gmin installed to provide path.
    No DC path from node `net06' to ground, Gmin installed to provide path.
        Further occurrences of this notice will be suppressed.
Fatal error found by spectre during topology check.
    FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit:
        V0:p (from net018 to net017)


Aggregate audit (11:42:48 PM, Tue Sep 3, 2019):
Time used: CPU = 274 ms, elapsed = 405 ms, util. = 67.6%.
Time spent in licensing: elapsed = 15.9 ms.
Peak memory used = 52.5 Mbytes.
Simulation started at: 11:42:47 PM, Tue Sep 3, 2019, ended at: 11:42:48 PM, Tue Sep 3, 2019, with elapsed time (wall clock): 405 ms.
spectre completes with 1 error, 3 warnings, and 6 notices.
spectre terminated prematurely due to fatal error.