Spectre (R) Circuit Simulator Version 21.1.0.546.isr13 64bit -- 4 Nov 2022 Copyright (C) 1989-2022 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. User: fvlupo Host: SeeQCNapoli HostID: E18F5121 PID: 621879 Memory available: 130.3122 GB physical: 134.8106 GB Linux : AlmaLinux release 8.7 (Stone Smilodon) CPU Type: AMD Ryzen 9 5950X 16-Core Processor Socket: Processors [Frequency] (Hyperthreaded Processor) 0: 0 [3400.0] (), 1 [3400.0] (), 2 [3400.0] (), 3 [4325.5] (), 4 [3400.0] () 5 [3400.0] (), 6 [3400.0] (), 7 [3400.0] (), 8 [3400.0] (), 9 [3400.0] () 10 [3400.0] (), 11 [3400.0] (), 12 [3400.0] (), 13 [3400.0] (), 14 [3400.0] () 15 [3400.0] (), 16 [4333.0] (), 17 [3400.0] (), 18 [3400.0] (), 19 [3400.0] () 20 [3400.0] (), 21 [3400.0] (), 22 [3400.0] (), 23 [3400.0] (), 24 [3400.0] () 25 [3400.0] (), 26 [3400.0] (), 27 [3400.0] (), 28 [3400.0] (), 29 [3400.0] () 30 [3400.0] (), 31 [3400.0] () System load averages (1min, 5min, 15min) : 3.6 %, 1.8 %, 1.4 % Hyperthreading is enabled Simulating `input.scs' on SeeQCNapoli at 1:27:14 PM, Mon Feb 20, 2023 (process id: 621879). Current working directory: /home/fvlupo/simulation/SEEQC_SFQ_CIRCUITS/jtl_test/maestro/results/maestro/ExplorerRun.0/1/SEEQC_SFQ_CIRCUITS_jtl_test_1/netlist Command line: /usr/local/cadence/installs/SPECTRE211/tools.lnx86/bin/spectre -64 \ input.scs +escchars +log ../psf/spectre.out -format psfxl -raw \ ../psf +lqtimeout 900 -maxw 5 -maxn 5 -env ade -ahdllibdir \ /home/fvlupo/simulation/SEEQC_SFQ_CIRCUITS/jtl_test/maestro/results/maestro/ExplorerRun.0/sharedData/CDS/ahdl/input.ahdlSimDB \ +logstatus Licensing Information: [13:27:14.072593] Configured Lic search path (21.01-s002): 5280@SeeQCNapoli Licensing Information: [13:27:14.131144] Periodic Lic check successful Loading /usr/local/cadence/installs/SPECTRE211/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... Loading /usr/local/cadence/installs/SPECTRE211/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ... Loading /usr/local/cadence/installs/SPECTRE211/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ... Loading /usr/local/cadence/installs/SPECTRE211/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ... Loading /usr/local/cadence/installs/SPECTRE211/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ... Reading file: /home/fvlupo/simulation/SEEQC_SFQ_CIRCUITS/jtl_test/maestro/results/maestro/ExplorerRun.0/1/SEEQC_SFQ_CIRCUITS_jtl_test_1/netlist/input.scs Reading file: /usr/local/cadence/installs/SPECTRE211/tools.lnx86/spectre/etc/configs/spectre.cfg Reading file: /home/fvlupo/Documents/SFQ/Circuits/SEEQC_SFQ_CIRCUITS/jj_shunt/veriloga/veriloga.va Reading file: /usr/local/cadence/installs/SPECTRE211/tools.lnx86/spectre/etc/ahdl/constants.vams Reading file: /usr/local/cadence/installs/SPECTRE211/tools.lnx86/spectre/etc/ahdl/disciplines.vams Reading file: /home/fvlupo/Documents/Supergate/Circuits/testLib/vgauss/veriloga/veriloga.va Time for NDB Parsing: CPU = 33.937 ms, elapsed = 95.799 ms. Time accumulated: CPU = 66.962 ms, elapsed = 95.8009 ms. Peak resident memory used = 148 Mbytes. Existing shared object for module jj_shunt is up to date. Installed compiled interface for jj_shunt. Existing shared object for module vgauss is up to date. Installed compiled interface for vgauss. Time for Elaboration: CPU = 7.285 ms, elapsed = 7.28798 ms. Time accumulated: CPU = 74.282 ms, elapsed = 103.124 ms. Peak resident memory used = 156 Mbytes. Notice from spectre during hierarchy flattening. The value 'psf' specified for the 'checklimitdest' option will no longer be supported in future releases. Use 'spectre -h' to see other recommended values for the 'checklimitdest' option. Warning from spectre during hierarchy flattening. WARNING (ASL-6206): "/home/fvlupo/Documents/Supergate/Circuits/testLib/vgauss/veriloga/veriloga.va" 19: I4: Number of initializer elements (1) does not agree with array size (1024) near line number 19. Correct the problem and try again. WARNING (ASL-6206): "/home/fvlupo/Documents/Supergate/Circuits/testLib/vgauss/veriloga/veriloga.va" 19: I4: Number of initializer elements (1) does not agree with array size (1024) near line number 19. Correct the problem and try again. Time for EDB Visiting: CPU = 256 us, elapsed = 262.022 us. Time accumulated: CPU = 74.577 ms, elapsed = 103.423 ms. Peak resident memory used = 158 Mbytes. Warning from spectre during initial setup. WARNING (SPECTRE-8059): `I0': `phase' No such output parameter, terminal, or internal node name. WARNING (SPECTRE-8287): Ignoring invalid item `I0:phase' in save statement. Notice from spectre during initial setup. Ignorevaref=yes is ignored since all nodes are connected to Verilog-A modules. Global user options: psfversion = 1.4.0 vabstol = 1e-06 iabstol = 1e-12 temp = -269.15 multithread = off gmin = 1e-12 rforce = 1 maxnotes = 5 maxwarns = 5 digits = 5 cols = 80 pivrel = 0.001 sensfile = ../psf/sens.output checklimitdest = psf save = allpub saveahdlvars = all reltol = 0.001 tnom = 27 scalem = 1 scale = 1 Scoped user options: Circuit inventory: nodes 4 inductor 3 isource 3 jj_shunt 3 vgauss 1 Analysis and control statement inventory: info 7 tran 1 Output statements: .probe 0 .measure 0 save 2 Time for parsing: CPU = 871 us, elapsed = 21.683 ms. Time accumulated: CPU = 75.478 ms, elapsed = 125.136 ms. Peak resident memory used = 161 Mbytes. ~~~~~~~~~~~~~~~~~~~~~~ Pre-Simulation Summary ~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~ ************************************************ Transient Analysis `tran': time = (0 s -> 20 ps) ************************************************ DC simulation time: CPU = 209 us, elapsed = 215.054 us. Opening the PSFXL file ../psf/tran.tran.tran ... Important parameter values: start = 0 s outputstart = 0 s stop = 20 ps step = 20 fs maxstep = 200 fs ic = all useprevic = no skipdc = no reltol = 100e-06 abstol(V) = 1 uV abstol(I) = 1 pA temp = -269.15 C tnom = 27 C tempeffects = all errpreset = conservative method = gear2only lteratio = 10 relref = alllocal cmin = 0 F gmin = 1 pS Output and IC/nodeset summary: save 3 (current) save 4 (voltage) others 268 tran: time = 512.7 fs (2.56 %), step = 30.36 fs (152 m%) tran: time = 1.516 ps (7.58 %), step = 61.85 fs (309 m%) tran: time = 2.632 ps (13.2 %), step = 158.7 fs (794 m%) tran: time = 3.562 ps (17.8 %), step = 137.7 fs (689 m%) tran: time = 4.652 ps (23.3 %), step = 200 fs (1 %) tran: time = 5.652 ps (28.3 %), step = 200 fs (1 %) tran: time = 6.652 ps (33.3 %), step = 200 fs (1 %) tran: time = 7.652 ps (38.3 %), step = 200 fs (1 %) tran: time = 8.652 ps (43.3 %), step = 200 fs (1 %) tran: time = 9.652 ps (48.3 %), step = 200 fs (1 %) tran: time = 10.65 ps (53.3 %), step = 200 fs (1 %) tran: time = 11.65 ps (58.3 %), step = 200 fs (1 %) tran: time = 12.65 ps (63.3 %), step = 200 fs (1 %) tran: time = 13.65 ps (68.3 %), step = 200 fs (1 %) tran: time = 14.65 ps (73.3 %), step = 200 fs (1 %) tran: time = 15.65 ps (78.3 %), step = 200 fs (1 %) tran: time = 16.65 ps (83.3 %), step = 200 fs (1 %) tran: time = 17.65 ps (88.3 %), step = 200 fs (1 %) tran: time = 18.65 ps (93.3 %), step = 200 fs (1 %) tran: time = 19.65 ps (98.3 %), step = 200 fs (1 %) Number of accepted tran steps = 146 Maximum value achieved for any signal of each quantity: V: V(I11:idt0) = 155.5 mV I: I(I11:lshunt_M_flow) = 6.7 uA ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Post-Transient Simulation Summary ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - To further speed up simulation, consider add ++aps on command line - Non-default settings that could significantly slow down simulation errpreset = conservative, default moderate ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ During simulation, the CPU load for active processors is : 0 (8.3 %) 7 (15.4 %) 10 (7.7 %) 11 (7.7 %) 12 (14.3 %) 16 (45.5 %) 19 (9.1 %) 22 (8.3 %) 23 (16.7 %) 30 (8.3 %) 31 (14.3 %) Total: 155.6% Initial condition solution time: CPU = 232 us, elapsed = 237.942 us. Intrinsic tran analysis time: CPU = 10.507 ms, elapsed = 16.4571 ms. Total time required for tran analysis `tran': CPU = 11.797 ms, elapsed = 17.7519 ms, util. = 66.5%. Time accumulated: CPU = 90.097 ms, elapsed = 145.719 ms. Peak resident memory used = 167 Mbytes. finalTimeOP: writing operating point information to rawfile. Opening the PSF file ../psf/finalTimeOP.info ... modelParameter: writing model parameter values to rawfile. Opening the PSF file ../psf/modelParameter.info ... element: writing instance parameter values to rawfile. Opening the PSF file ../psf/element.info ... outputParameter: writing output parameter values to rawfile. Opening the PSF file ../psf/outputParameter.info ... designParamVals: writing netlist parameters to rawfile. Opening the PSFASCII file ../psf/designParamVals.info ... primitives: writing primitives to rawfile. Opening the PSFASCII file ../psf/primitives.info.primitives ... subckts: writing subcircuits to rawfile. Opening the PSFASCII file ../psf/subckts.info.subckts ... Licensing Information: Lic Summary: [13:27:14.275016] Cdslmd servers:5280@SeeQCNapoli [13:27:14.275025] Feature usage summary: [13:27:14.275025] Virtuoso_Spectre Aggregate audit (1:27:14 PM, Mon Feb 20, 2023): Time used: CPU = 93.4 ms, elapsed = 224 ms, util. = 41.7%. Time spent in licensing: elapsed = 12.5 ms, percentage of total = 5.56%. Peak memory used = 168 Mbytes. Simulation started at: 1:27:14 PM, Mon Feb 20, 2023, ended at: 1:27:14 PM, Mon Feb 20, 2023, with elapsed time (wall clock): 224 ms. spectre completes with 0 errors, 4 warnings, and 3 notices. ********* LOG ENDS ************** ** **