// VerilogA for sdd5e_TB, ten_bit_word_gen_triggered, veriloga

// Crude code to provide example of subcircuit to read 10 bit bus from file
// and provide subsequent 10-bit output on rising edge of input clkin
// Missing many features and insufficient file checking...but works..
// sml 8/17/2022 v1.0

`include "constants.vams"
`include "disciplines.vams"

module ten_bit_word_gen_triggered(v0,v1,v2,v3,v4,v5,v6,v7,v8,v9,clkin);
input clkin;
output v0,v1,v2,v3,v4,v5,v6,v7,v8,v9;
electrical v0,v1,v2,v3,v4,v5,v6,v7,v8,v9,clkin;

integer file;
integer count, count0,count1,count2,count3,count4,count5,count6,count7,count8,count9;
integer input_string;

real tdelay, trise, tfall, vthreshold;
real val0, val1, val2, val3, val4, val5, val6, val7,val8,val9;
real v0_int,v1_int,v2_int,v3_int,v4_int,v5_int,v6_int,v7_int,v8_int,v9_int;

analog begin
     @(initial_step) begin
         count0 = 0;
         count1 = 0;
         count2 = 0;
         count3 = 0;
         count4 = 0;
         count5 = 0;
         count6 = 0;
         count7 = 0;
         count8 = 0;
         count9 = 0;
         tdelay = 0;
         trise = 100e-12;
         tfall = 100e-12;
         vthreshold = 0.50;

                                  
        file = $fopen("/project/sdd5e/users/smlogan/cds/omar_10bit_bus_example.txt.csv", "r");
                               
        if ( $fscanf(file, "%f,%f,%f,%f,%f,%f,%f,%f,%f,%f",val0,val1,val2,val3,val4,val5,val6,val7,val8,val9 ) == 10 ) begin                                                     
           count0 = val0;
           count1 = val1;
           count2 = val2;
           count3 = val3;
           count4 = val4;
           count5 = val5;
           count6 = val6;
           count7 = val7;
           count8 = val8;
           count9 = val9;         
         end
            v0_int = val0;
            v1_int = val1;
            v2_int = val2;
            v3_int = val3;
            v4_int = val4;
            v5_int = val5;
            v6_int = val6;
            v7_int = val7;
            v8_int = val8;
            v9_int = val9;
   end

@ cross(V(clkin)-vthreshold, +1) begin

        count0 = 0;
        count1 = 0;
        count2 = 0;
        count3 = 0;
        count4 = 0;
        count5 = 0;
        count6 = 0;
        count7 = 0;
        count8 = 0;
        count9 = 0;
        trise = 100e-12;
        tfall = 100e-12;
        vthreshold = 0.50;

     if ( $fscanf(file, "%f,%f,%f,%f,%f,%f,%f,%f,%f,%f",val0,val1,val2,val3,val4,val5,val6,val7,val8,val9 ) == 10 ) begin                                                     
        count0 = val0;
        count1 = val1;
        count2 = val2;
        count3 = val3;
        count4 = val4;
        count5 = val5;
        count6 = val6;
        count7 = val7; 
        count8 = val8;
        count9 = val9;        
      end
         v0_int = val0;
         v1_int = val1;
         v2_int = val2;
         v3_int = val3;
         v4_int = val4;
         v5_int = val5;
         v6_int = val6;
         v7_int = val7;
         v8_int = val8;
         v9_int = val9;
end
   V(v0) <+transition(v0_int, tdelay, trise, tfall);                                       
   V(v1) <+transition(v1_int, tdelay, trise, tfall); 
   V(v2) <+transition(v2_int, tdelay, trise, tfall);
   V(v3) <+transition(v3_int, tdelay, trise, tfall);
   V(v4) <+transition(v4_int, tdelay, trise, tfall);
   V(v5) <+transition(v5_int, tdelay, trise, tfall);
   V(v6) <+transition(v6_int, tdelay, trise, tfall);
   V(v7) <+transition(v7_int, tdelay, trise, tfall);
   V(v8) <+transition(v8_int, tdelay, trise, tfall);
   V(v9) <+transition(v9_int, tdelay, trise, tfall);

$fclose( file );
end
                        
endmodule