// Point Netlist Generated on: Dec 28 19:49:26 2021
// Generated for: spectre
// Design Netlist Generated on: Dec 28 19:49:26 2021
// Design library name: behavioral_blocks
// Design cell name: tb_test_parent
// Design view name: schematic
simulator lang=spectre
global 0
include "$SPECTRE_MODEL_PATH/design_wrapper.lib.scs" section=tt_pre
parameters wireopt=11

// Library name: behavioral_blocks
// Cell name: tb_test_parent
// View name: schematic
I0 (net1 net2) test_parent N=9
simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 \
    vthmod=vthcc ivthn=300e-9 ivthp=70e-9 ivthw=0 ivthl=0 maxnotes=5 \
    maxwarns=5 digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf vdsatmod=gds 
tran tran stop=10n errpreset=conservative write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub
ahdl_include "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/test_parent/veriloga/veriloga.va"
ahdl_include "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/test1/veriloga/veriloga.va"