// VerilogA for VerilogA_layout_ring_osc, VerilogA_Layout_test, veriloga

`include "constants.vams"
`include "disciplines.vams"

module VerilogA_RDUC_V2_Power_test_V2 (
inout electrical VDD,
inout electrical VSS,
input electrical INV_IN,
output electrical INV_OUT,
output electrical out,
output electrical [0:110] intern
);

parameter integer N_stage = 3;
parameter integer tech = 1;
parameter integer test = 1;
parameter integer stacked = 1 from [1:500];
parameter integer turned_on = 1 from [0:500];

electrical [2:0] phi;
electrical [stacked-1:0] EN;


// initialize the instances before the generate blocks
RDUC_INV_V2 I4(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));
RDUC_INV_V2_HVT I5(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));
RDUC_INV_V2_LVT I6(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));
RDUC_INV_V2_R_big I7(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));
RDUC_INV_V2_R_small I8(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));

genvar stack; 
genvar i; 
genvar j;
genvar l;
genvar m;

generate 
if (tech == 1) begin
	if (N_stage != 1 && N_stage%2 == 1 && N_stage <= 26)begin         
		for (stack = stacked-1; stack>=0; stack = stack -1) begin        // for loop to generate the correct amount of stacked delay lines
			for (i = 1;i<= N_stage-1;i=i+1) begin                    // for loop to generate the delay line with the correct amount of inverters
				RDUC_INV_V2 I0(.VDD(VDD),.VSS(VSS),.IN(intern[i]),.OUT(intern[i+1]),.EN(EN[stack]));
			end		
			for(j=N_stage;j<=N_stage;j=j+1) begin
				RDUC_INV_V2 I1(.VDD(VDD),.VSS(VSS),.IN(intern[j]),.OUT(out),.EN(EN[stack]));       // connecting the output of the last inverter to the output of the block    
			end 
		end

		// Enable the correct amount of inverters to get frequency tuning
		for (l = stacked-1; l>=stacked-turned_on; l = l -1) begin
			analog V(EN[l], VSS) <+ V(VDD, VSS);
		end

		for (m = stacked-turned_on-1; m>=0; m = m -1) begin
			analog V(EN[m], VSS) <+ 0;
		end

		if (test == 1) begin
			analog V(out,intern[1]) <+0;		// connecting the output to the first signal to create the feedback loop of the RO
		end
	end
end
endgenerate
endmodule