// Generated for: spectre // Generated on: Aug 14 21:28:57 2021 // Design library name: PHD22 // Design cell name: switching // Design view name: schematic simulator lang=spectre global 0 parameters r=50 frf=50M f=50000k c=1000n DC=0 Amp=1 Ac_mag=0 // Library name: PHD22 // Cell name: switching // View name: schematic W0 (Prt net02 clk 0) relay vt1=1m vt2=500.0m ropen=1T rclosed=1.0 C1 (net02 0) capacitor c=c V1 (clk 0) vsource type=pulse val0=0 val1=500.0m period=1/f width=1/(2*f) \ fundname="CLK" PORT1 (Prt 0) port r=r dc=DC/2 type=sine freq=frf ampl=Amp/2 mag=Ac_mag/2 \ isnoisy=yes simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ checklimitdest=psf pss pss fund=50M harms=20 errpreset=liberal autotstab=yes + saveinit=yes method=gear2only tstabmethod=gear2only maxacfreq=50G + annotate=status pnoise ( net02 0 ) pnoise start=1 stop=25M + maxsideband=1000 iprobe=PORT1 refsideband=0 + noisetype=timeaverage noiseout=[usb] annotate=status modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile saveOptions options save=all