// Generated for: spectre // Generated on: Mar 22 10:31:14 2018 // Design library name: DESIGN // Design cell name: TB_comparators // Design view name: schematic simulator lang=spectre global 0 parameters en_sine=0 en_step=0 en_pulse=1 frequency=1k Vos=-173u Cload=1p \ en_1v5=1 en_5v=1 Idd=250n PSRR_en=0 vdd_1v5=1.5 vdd_5v0=3.8 vref=0.75 include "active.scs" section=tt include "passive.scs" section=pass_nom include "Device_without_mismatch_checks.scs" // Library name: disc13ip // Cell name: nmos5v_iso // View name: schematic subckt nmos5v_iso B D DN G S SUB parameters area_nblpsubhvpw_dio_iso=1.48225e-10 \ pj_nblpsubhvpw_dio_iso=4.87e-05 multiGL=(1) \ area_pwnblhvnw_dio_iso=1.2775e-11 pj_pwnblhvnw_dio_iso=1.43e-05 \ w=2u l=600n fingers=1 as=8.2e-13 ad=8.2e-13 ps=4.82u pd=4.82u \ sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 nrd=0.105 nrs=0.105 \ mismatchflag=1 sigma=1 D1 (SUB DN) nblpsubhvpw_dio_iso area=area_nblpsubhvpw_dio_iso \ pj=pj_nblpsubhvpw_dio_iso m=multiGL D0 (B DN) pwnblhvnw_dio_iso area=area_pwnblhvnw_dio_iso \ pj=pj_pwnblhvnw_dio_iso m=multiGL M0 (D G S B) nch_tgo5_mac w=w l=l nf=fingers as=as ad=ad ps=ps pd=pd \ sa=sa sb=sb sd=sd nrd=nrd nrs=nrs multi=multiGL \ mismatchflag=mismatchflag sigma=sigma ends nmos5v_iso // End of subcircuit definition. // Library name: d50r3s // Cell name: v5inv_1x // View name: schematic subckt v5inv_1x IN0 Y inh_dig_vdd inh_dig_vss inh_nbulk M1 (Y IN0 inh_dig_vdd inh_dig_vdd) pch_tgo5_mac w=1.13u l=600n nf=1 \ as=4.068e-13 ad=4.068e-13 ps=2.98u pd=2.98u sa=4.1e-07 sb=4.1e-07 \ sd=4.2e-07 nrd=0.185841 nrs=0.185841 multi=1 mismatchflag=1 \ sigma=1 M0 (Y IN0 inh_dig_vss inh_nbulk) nch_tgo5_mac w=800n l=600n nf=1 \ as=2.88e-13 ad=2.88e-13 ps=2.32u pd=2.32u sa=4.1e-07 sb=4.1e-07 \ sd=4.2e-07 nrd=0.2625 nrs=0.2625 multi=1 mismatchflag=1 sigma=1 ends v5inv_1x // End of subcircuit definition. // Library name: DESIGN // Cell name: comparator // View name: schematic subckt comparator en_1v5 ibias in_n in_p out vdd vss M6 (out out_1st vss vss) nch_tgo5_mac w=1.92u l=600n nf=1 as=7.872e-13 \ ad=7.872e-13 ps=4.66u pd=4.66u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \ nrd=0.109375 nrs=0.109375 multi=2 mismatchflag=1 sigma=1 M3 (loads loads vss vss) nch_tgo5_mac w=3u l=10u nf=1 as=1.23e-12 \ ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \ nrd=0.07 nrs=0.07 multi=2 mismatchflag=1 sigma=1 M4 (out_1st loads vss vss) nch_tgo5_mac w=3u l=10u nf=1 as=1.23e-12 \ ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \ nrd=0.07 nrs=0.07 multi=2 mismatchflag=1 sigma=1 M14 (pmirror ibias vss vss) nch_tgo5_mac w=10u l=10u nf=1 as=4.1e-12 \ ad=4.1e-12 ps=20.82u pd=20.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \ nrd=0.021 nrs=0.021 multi=1 mismatchflag=1 sigma=1 M0 (ibias ibias vss vss) nch_tgo5_mac w=10u l=10u nf=1 as=4.1e-12 \ ad=4.1e-12 ps=20.82u pd=20.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \ nrd=0.021 nrs=0.021 multi=1 mismatchflag=1 sigma=1 Npdsimfsto (vss out_1st vdd_5v0 en_n_5v vss vss) nmos5v_iso \ area_nblpsubhvpw_dio_iso=1.48225e-10 \ pj_nblpsubhvpw_dio_iso=4.87e-05 multiGL=(1) \ area_pwnblhvnw_dio_iso=1.2775e-11 pj_pwnblhvnw_dio_iso=1.43e-05 \ w=1u l=1u fingers=1 as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u \ sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 nrd=0.21 nrs=0.21 mismatchflag=1 \ sigma=1 Npdleg1 (vss loads vdd_5v0 en_n_5v vss vss) nmos5v_iso \ area_nblpsubhvpw_dio_iso=1.48225e-10 \ pj_nblpsubhvpw_dio_iso=4.87e-05 multiGL=(1) \ area_pwnblhvnw_dio_iso=1.2775e-11 pj_pwnblhvnw_dio_iso=1.43e-05 \ w=1u l=1u fingers=1 as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u \ sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 nrd=0.21 nrs=0.21 mismatchflag=1 \ sigma=1 N0 (vss ibias vdd_5v0 en_n_5v vss vss) nmos5v_iso \ area_nblpsubhvpw_dio_iso=1.48225e-10 \ pj_nblpsubhvpw_dio_iso=4.87e-05 multiGL=(1) \ area_pwnblhvnw_dio_iso=1.2775e-11 pj_pwnblhvnw_dio_iso=1.43e-05 \ w=1u l=1u fingers=1 as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u \ sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 nrd=0.21 nrs=0.21 mismatchflag=1 \ sigma=1 Ppusimovin (pmirror en vdd_5v0 vdd_5v0) pch_tgo5_mac w=1u l=1u nf=1 \ as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u sa=4.1e-07 sb=4.1e-07 \ sd=4.2e-07 nrd=0.21 nrs=0.21 multi=1 mismatchflag=1 sigma=1 P_pup_tail (tail en vdd_5v0 vdd_5v0) pch_tgo5_mac w=1u l=1u nf=1 \ as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u sa=4.1e-07 sb=4.1e-07 \ sd=4.2e-07 nrd=0.21 nrs=0.21 multi=1 mismatchflag=1 sigma=1 M13 (in_n en vdd_5v0 vdd_5v0) pch_tgo5_mac w=1u l=1u nf=1 as=4.1e-13 \ ad=4.1e-13 ps=2.82u pd=2.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \ nrd=0.21 nrs=0.21 multi=1 mismatchflag=1 sigma=1 M12 (in_p en vdd_5v0 vdd_5v0) pch_tgo5_mac w=1u l=1u nf=1 as=4.1e-13 \ ad=4.1e-13 ps=2.82u pd=2.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \ nrd=0.21 nrs=0.21 multi=1 mismatchflag=1 sigma=1 M7 (out pmirror vdd vdd) pch_tgo5_mac w=3u l=12.0u nf=1 as=1.23e-12 \ ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \ nrd=0.07 nrs=0.07 multi=16 mismatchflag=1 sigma=1 M5 (tail pmirror vdd vdd) pch_tgo5_mac w=3u l=12.0u nf=1 as=1.23e-12 \ ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \ nrd=0.07 nrs=0.07 multi=4 mismatchflag=1 sigma=1 M9 (pmirror pmirror vdd vdd) pch_tgo5_mac w=3u l=12.0u nf=1 \ as=1.23e-12 ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 \ sd=4.2e-07 nrd=0.07 nrs=0.07 multi=4 mismatchflag=1 sigma=1 M2 (out_1st in_p tail tail) pch_tgo5_mac w=20u l=2u nf=2 as=8.2e-12 \ ad=4.2e-12 ps=41.64u pd=20.84u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \ nrd=0.0105 nrs=0.0105 multi=2 mismatchflag=1 sigma=1 M1 (loads in_n tail tail) pch_tgo5_mac w=20u l=2u nf=2 as=8.2e-12 \ ad=4.2e-12 ps=41.64u pd=20.84u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \ nrd=0.0105 nrs=0.0105 multi=2 mismatchflag=1 sigma=1 I7 (en_n_5v en vdd vss vss) v5inv_1x I5 (en_1v5 en_n_5v vdd vss vss) v5inv_1x ends comparator // End of subcircuit definition. // Library name: DESIGN // Cell name: TB_comparators // View name: schematic W7 (pulse stimuli 0 net06) relay vt1=3 vt2=0 ropen=1T rclosed=100n V10 (net06 0) vsource dc=en_pulse*1.5 type=dc V3 (vref 0) vsource dc=vref type=dc V11 (en_5v 0) vsource dc=en_5v*vdd_5v0 type=dc V13 (en_1v5 0) vsource dc=en_1v5*vdd_5v0 type=dc V1 (vss 0) vsource dc=0 mag=PSRR_en type=dc V0 (vdd_1v5 0) vsource dc=vdd_1v5 type=dc V14 (vdd_5v0 0) vsource dc=vdd_5v0 mag=PSRR_en type=dc V4 (sine 0) vsource dc=vref type=sine ampl=100.0m sinephase=0 \ freq=frequency C0 (out vss) capacitor c=Cload I12 (vdd_5v0 net11) isource dc=Idd type=dc Icomp (en_1v5 net11 stimuli vref out vdd_5v0 vss) comparator V2 (pulse 0) vsource dc=vref type=pulse val0=0 val1=vdd_1v5 period=2m \ delay=500u rise=50n fall=50n width=1.5ms V6 (step 0) vsource dc=vref type=pwl wave=[ 0 0 100u 0 ] simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=27 scalem=1.0 scale=1 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ dochecklimit=yes checklimitdest=both dcOpCheckLimit checklimit checkallasserts=yes severity=none dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status dcOpInfo info what=oppoint where=rawfile tranCheckLimit checklimit checkallasserts=yes severity=none tran tran stop=15m errpreset=moderate write="spectre.ic" \ writefinal="spectre.fc" annotate=status maxiters=5 finalTimeOP info what=oppoint where=rawfile modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile asserts info what=assert where=rawfile saveOptions options save=all currents=all subcktprobelvl=2