// VerilogA for behavioral_blocks, fopen_issue, veriloga

`include "constants.vams"
`include "disciplines.vams"


module fopen_issue(in, out);

input in;
output out;

voltage in, out;

parameter integer write_to_file = 1 from [0:1];
parameter string filename_base = "~/Desktop/file_with_saved_values";

integer count;
integer fid;
string filename_mod;

analog begin
	@(initial_step) begin	
		$swrite(filename_mod, "%s.%M.vals", filename_base);
		fid = $fopen(filename_mod, "r");
		if(fid != 0) begin
			count = 1;
			while(fid) begin
				$display("fopen_issue %M: file %s already found, will rename and retry", filename_mod);
				$fclose(fid);
				$swrite(filename_mod, "%s_%d.%M.vals", filename_base, count);
				count = count+1;
				fid = $fopen(filename_mod, "r");
			end	// while end
		end	// if(fid) end
		$fclose(fid);
	end	// @(initial_step) end
	@(final_step) begin
		fid = $fopen(filename_mod, "w");
		$display("fopen_issue %M: Final values will be written to file \"%s\".", filename_mod);
		$fclose(fid);
	end	// @(final_step) end
end	// analog end

endmodule