// Generated for: spectre
// Generated on: Dec  1 16:17:16 2019
// Design library name: lab3
// Design cell name: param_inverter_test
// Design view name: schematic
simulator lang=spectre
global 0
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_bip
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_dio
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_dio_33
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_mim
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_dio_dnw
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_dio_18
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_bip_npn
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_33
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_rfrtmom
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_mos_cap_25
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_18
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_disres
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_res
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_dio_na
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_rfmos_33
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_dio_hvt
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_rfmvar
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_rfmos_18
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_na
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_dio_na33
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_dio_lvt
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_rfres_sa
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_na33
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_dio_esd
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_rfmim
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_dio_25od33
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_25od33
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_mos_cap
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_dio_25
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_dio_25ud18
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_25
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_rfmos
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_25ud18
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_dio_na25od33
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_rfjvar
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_rfmos_25
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_rtmom
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_na25od33
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_dio_na25
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_rfres_rpo
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_hvt
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_rfind
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_rfmvar_25
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_na25
include "/CMC/kits/tsmc_65nm/CRN65GP/TN65CMSP018K3_V1.0C/tsmcN65/../models/spectre/crn65gplus_2d5_lk_v1d0.scs" section=tt_lvt

// Library name: lab3
// Cell name: param_inverter
// View name: schematic
subckt param_inverter A Y
parameters width=130n
    M0 (Y A 0 0) nch l=65.0n w=width*1 m=1 nf=1 sd=200n \
        ad=((1-int(1/2)*2)*(1.75e-07+((1-1)*2e-07)/2+0)+(1+1-int((1+1)/2)*2)*((1/2)*2e-07))*width \
        as=((1-int(1/2)*2)*(1.75e-07+((1-1)*2e-07)/2+0)+(1+1-int((1+1)/2)*2)*(1.75e-07+1.75e-07+(1/2-1)*2e-07+0+0))*width \
        pd=(1-int(1/2)*2)*((1.75e-07+((1-1)*2e-07)/2+0)*2+(1+1)*width)+(1+1-int((1+1)/2)*2)*(((1/2)*2e-07)*2+1*width) \
        ps=(1-int(1/2)*2)*((1.75e-07+((1-1)*2e-07)/2+0)*2+(1+1)*width)+(1+1-int((1+1)/2)*2)*((1.75e-07+1.75e-07+(1/2-1)*2e-07+0+0)*2+(1+2)*width) \
        nrd=(1-int(1/2)*2)*(1e-07*1e-07/(1e-07+1e-07*(1-1))/width)+((1+1)nt((1+1)/2)*2)*(1e-07/1/width) \
        nrs=(1-int(1/2)*2)*(1e-07*1e-07/(1e-07+1e-07*(1-1))/width)+((1+1)nt((1+1)/2)*2)*(1e-07*1e-07*1e-07/(1e-07*1e-07*(1-2)+1e-07*(1e-07+1e-07))/width) \
        sa=175.00n sb=175.00n sca=0 scb=0 scc=0
    M1 (Y A net8 net8) pch l=65.0n w=width*2*1 m=1 nf=1 sd=200n \
        ad=((1-int(1/2)*2)*(1.75e-07+((1-1)*2e-07)/2+0)+(1+1-int((1+1)/2)*2)*((1/2)*2e-07))*width*2 \
        as=((1-int(1/2)*2)*(1.75e-07+((1-1)*2e-07)/2+0)+(1+1-int((1+1)/2)*2)*(1.75e-07+1.75e-07+(1/2-1)*2e-07+0+0))*width*2 \
        pd=(1-int(1/2)*2)*((1.75e-07+((1-1)*2e-07)/2+0)*2+(1+1)*width*2)+(1+1-int((1+1)/2)*2)*(((1/2)*2e-07)*2+1*width*2) \
        ps=(1-int(1/2)*2)*((1.75e-07+((1-1)*2e-07)/2+0)*2+(1+1)*width*2)+(1+1-int((1+1)/2)*2)*((1.75e-07+1.75e-07+(1/2-1)*2e-07+0+0)*2+(1+2)*width*2) \
        nrd=(1-int(1/2)*2)*(1e-07*1e-07/(1e-07+1e-07*(1-1))/width*2)t((1+-int((1+1)/3)*2)*(1e-07/1/width*2) \
        nrs=(1-int(1/2)*2)*(1e-07*1e-07/(1e-07+1e-07*(1-1))/width*2)t((1+-int((1+1)/2)*2)*(1e-07*1e-07*1e-07/(1e-07*1e-07*(1-2)+1e-07*(1e-07+1e-07))/width*2) \
        sa=175.00n sb=175.00n sca=0 scb=0 scc=0
    V0 (net8 0) vsource dc=1 type=dc
ends param_inverter
// End of subcircuit definition.

// Library name: lab3
// Cell name: param_inverter_test
// View name: schematic
I1 (net5 Y) param_inverter width=260n
I0 (A net5) param_inverter width=130n
include "./_graphical_stimuli.scs"
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf 
tran tran stop=4n errpreset=moderate write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
saveOptions options save=allpub