// VerilogA for behavioral_blocks, mod_counter, veriloga

`include "constants.vams"
`include "disciplines.vams"

module mod_counter(clk, out, carry);

input clk;
output out, carry;
electrical clk, out, carry;

parameter real out_t_delay = 0 from [0:inf);
parameter real out_t_transition = 10f from [0:inf);

parameter integer inherent_clock = 1 from [0:2];
parameter real first_sample_t_delay = 0 from [0:inf);

parameter real clk_f = 3e9;
parameter real vdd = 0.8 from [0:5];
parameter real vclk_threshold = 0.4 from [0:vdd];
parameter integer clk_dir = 1 from [-1:1];

parameter integer modulo = 6 from [0:inf);

integer out_val = 0, carry_val = 0;

analog	@(initial_step)	$display("Modcounter %M: Instance parameters inhereted are:\n\t\tout_t_delay = %g\n\t\tout_t_transition = %g\n\t\tinherent_clock = %d\n\t\tfirst_sample_t_delay = %g\n\t\t\clk_f = %g\n\t\t\vdd = %g\n\t\t\vclk_threshold = %g\n\t\tclk_dir = %d\n\t\tmodulo = %d\n", out_t_delay, out_t_transition, inherent_clock, first_sample_t_delay, clk_f, vdd, vclk_threshold, clk_dir, modulo);

generate
	if (inherent_clock == 1)	begin
		analog	@(initial_step)	$display("Modcounter %M: Entering Inherent clock mode because inherent_clk = %d", inherent_clock);
		case (1)
			(clk_dir == -1) :	begin
									analog	@(initial_step)	$display("Modcounter %M: Inherent clock mode falling edge\n\n");
									analog 	@(timer(first_sample_t_delay+0.5/clk_f,1.0/clk_f))	begin	out_val = (out_val + 1) % modulo; carry_val = (out_val == 0); end
								end
			(clk_dir ==  0) :	begin
									analog	@(initial_step)	$display("Modcounter %M: Inherent clock mode dual edge\n\n");
									analog	@(timer(first_sample_t_delay,0.5/clk_f))			begin	out_val = (out_val + 1) % modulo; carry_val = (out_val == 0); end
								end
			(clk_dir ==  1) :	begin
									analog	@(initial_step)	$display("Modcounter %M: Inherent clock mode rising edge\n\n");
									analog 	@(timer(first_sample_t_delay,1.0/clk_f))			begin	out_val = (out_val + 1) % modulo; carry_val = (out_val == 0); end
								end
		endcase
	end


	else begin
		analog	@(initial_step)	$display("Modcounter %M: Enterinng External clock mode because inherent_clk = %d", inherent_clock);
		if (first_sample_t_delay > 0)	begin
			analog	@(initial_step)	$display("Modcounter %M: Delayed External clock mode");
			electrical int_del_clk;
			analog	V(int_del_clk) <+ absdelay(V(clk),first_sample_t_delay);
			case (1)
				(clk_dir == -1) :	begin
										analog	@(initial_step)	$display("Modcounter %M: Delayed External clock mode falling edge\n\n");
										analog	@(above(vclk_threshold-1e-3-V(int_del_clk))) begin	out_val = (out_val + 1) % modulo;	carry_val = (out_val == 0); end
									end
				(clk_dir ==  0) :	begin
										analog	@(initial_step)	$display("Modcounter %M: Delayed External clock mode dual edge\n\n");
										analog	@(above(vclk_threshold-1e-3-V(int_del_clk)) or above(V(int_del_clk)-vclk_threshold)) begin	out_val = (out_val + 1) % modulo;	carry_val = (out_val == 0); end
									end
				(clk_dir ==  1) :	begin
										analog	@(initial_step)	$display("Modcounter %M: Delayed External clock mode rising edge\n\n");
										analog	@(above(V(int_del_clk)-vclk_threshold)) begin	out_val = (out_val + 1) % modulo;	carry_val = (out_val == 0); end
									end
			endcase
		end
		else	begin
			analog	@(initial_step)	$display("Modcounter %M: Non delayed External clock mode");
			case (1)
				(clk_dir == -1) :	begin
										analog	@(initial_step)	$display("Modcounter %M: Non delayed External clock mode falling edge\n\n");
										analog	@(above(vclk_threshold-1e-3-V(clk))) begin	out_val = (out_val + 1) % modulo;	carry_val = (out_val == 0); end
									end
				(clk_dir ==  0) :	begin
										analog	@(initial_step)	$display("Modcounter %M: Non delayed External clock mode dual edge\n\n");
										analog	@(above(vclk_threshold-1e-3-V(clk)) or above(V(clk)-vclk_threshold)) begin	out_val = (out_val + 1) % modulo;	carry_val = (out_val == 0); end
									end
				(clk_dir ==  1) :	begin
										analog	@(initial_step)	$display("Modcounter %M: Non delayed External clock mode rising edge\n\n");	
										analog	@(above(V(clk)-vclk_threshold)) begin	out_val = (out_val + 1) % modulo;	carry_val = (out_val == 0); end
									end
			endcase
		end
	end


	analog begin
		V(out)		<+ transition(out_val,	out_t_delay, out_t_transition, out_t_transition);
		V(carry)	<+ transition(vdd*carry_val,	out_t_delay, out_t_transition, out_t_transition);
	end
endgenerate

endmodule