// VerilogA for behavioral_blocks, mth_residue_estimator, veriloga

`include "constants.vams"
`include "disciplines.vams"

module mth_residue_estimator(in, sk_corr, sk_mult, clk_fs, clk_fs_o_Rp1, kth_estim_all_done, out, coeff_done);

input in, sk_corr, sk_mult, clk_fs, clk_fs_o_Rp1, kth_estim_all_done;
output out, coeff_done;
electrical in, sk_corr, sk_mult, clk_fs, clk_fs_o_Rp1, kth_estim_all_done, out, coeff_done;

parameter real out_t_delay = 0 from [0:inf);
parameter real out_t_transition = 10f from [0:inf);
parameter real int_clk_skew = out_t_transition from [0:inf);

parameter integer inherent_clock = 1 from [0:1];
parameter real first_sample_t_delay = 0 from [0:inf);

parameter real clk_f = 3e9;
parameter real vdd = 0.8 from [0:5];
parameter real vclk_threshold = 0.4 from [0:vdd];

parameter integer R = 5 from [0:inf);

electrical latch_clk;
electrical accum_clk, address;

	lookup_table # (.out_t_delay(out_t_delay), .out_t_transition(out_t_transition), .inherent_clock(inherent_clock), .first_sample_t_delay(first_sample_t_delay+int_clk_skew), .clk_f(clk_f), 	.vdd(vdd), .vclk_threshold(vclk_threshold), .size(R+1)) I_ACCUM_CLK_GEN_LUT (.address(address), .rst(latch_clk), .sk_n(sk_corr), .accum_clk(accum_clk));
	mod_counter # (.out_t_delay(out_t_delay), .out_t_transition(out_t_transition), .inherent_clock(inherent_clock), .first_sample_t_delay(first_sample_t_delay), .clk_f(clk_f), 	.vdd(vdd), .vclk_threshold(vclk_threshold), .clk_dir(-1), .modulo(R+1)) I_ACCUM_CLK_ADDRESS_GEN (.clk(clk_fs), .out(address));
	mod_counter # (.out_t_transition(out_t_transition), .inherent_clock(0), .first_sample_t_delay(0), .clk_f(15e9), .clk_dir(1), .modulo(R+1)) I_LATCH_CLK_GEN (.clk(accum_clk), .carry(coeff_done));

endmodule