// Library name: PHD22
// Cell name: switching
// View name: schematic
W0 (Prt net02 clk 0) relay vt1=1m vt2=500.0m ropen=1T rclosed=1.0
C1 (net02 0) capacitor c=c
V1 (clk 0) vsource type=pulse val0=0 val1=500.0m period=1/f width=1/(2*f) \
        fundname="CLK"
PORT1 (Prt 0) port r=r dc=DC/2 type=sine freq=frf ampl=Amp/2 mag=Ac_mag/2 \
        isnoisy=yes