// Point Netlist Generated on: Dec 23 10:04:40 2021
// Generated for: spectre
// Design Netlist Generated on: Dec 23 10:04:40 2021
// Design library name: altair_DAC
// Design cell name: tb_residue_estimator
// Design view name: schematic
simulator lang=spectre
global 0
include "$SPECTRE_MODEL_PATH/design_wrapper.lib.scs" section=tt_pre
parameters R=5 clk_dir=-1 clk_f=3G clk_tf=(0.02 / clk_f) clk_tr=(0.02 / \
    clk_f) sim_tran_tstp=(1000 / clk_f)

// Library name: altair_DAC
// Cell name: tb_residue_estimator
// View name: schematic
V3 (sk_n 0) vsource dc=1 type=dc
V5 (net1 0) vsource dc=1 type=dc
V37 (clk_fs 0) vsource type=pulse val0=0 val1=800.0m period=1/clk_f \
        delay=-clk_tr/2 rise=clk_tr fall=clk_tf \
        width=0.5*((1/clk_f)-(clk_tr)-(clk_tf))
I5 (net5 out_inh carry_inh) mod_counter out_t_delay=0 \
        out_t_transition=clk_tr inherent_clock=1 \
        first_sample_t_delay=clk_tr clk_f=clk_f vdd=0.8 vclk_threshold=0.4 \
        clk_dir=clk_dir modulo=6
I4 (sk_n out_ext_nondel carry_ext_nondel) mod_counter out_t_delay=0 \
        out_t_transition=clk_tr inherent_clock=0 first_sample_t_delay=0 \
        clk_f=clk_f vdd=0.8 vclk_threshold=0.4 clk_dir=clk_dir modulo=6
I1 (sk_n out_ext carry_ext) mod_counter out_t_delay=0 \
        out_t_transition=clk_tr inherent_clock=0 \
        first_sample_t_delay=clk_tr clk_f=clk_f vdd=0.8 vclk_threshold=0.4 \
        clk_dir=clk_dir modulo=6
simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 \
    vthmod=vthcc ivthn=300e-9 ivthp=70e-9 ivthw=0 ivthl=0 maxnotes=5 \
    maxwarns=5 digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf vdsatmod=gds 
tran tran stop=sim_tran_tstp errpreset=conservative write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=all saveahdlvars=all
ahdl_include "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/mod_counter/veriloga/veriloga.va"