Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator Version 11.1.0.509.isr14 64bit -- 14 Aug 2012 Copyright (C) 1989-2012 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. Protected by U.S. Patents: 5,610,847; 5,790,436; 5,812,431; 5,859,785; 5,949,992; 5,987,238; 6,088,523; 6,101,323; 6,151,698; 6,181,754; 6,260,176; 6,278,964; 6,349,272; 6,374,390; 6,493,849; 6,504,885; 6,618,837; 6,636,839; 6,778,025; 6,832,358; 6,851,097; 6,928,626; 7,024,652; 7,035,782; 7,085,700; 7,143,021; 7,493,240; 7,571,401. Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. User: qnehal Host: icslsrv3.ee.ucla.edu HostID: 43A48BC2 PID: 21797 Memory available: 121.0790 GB physical: 270.5638 GB CPU Type: Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz Processor PhysicalID CoreID Frequency 0 0 0 2900.1 1 1 0 2900.1 2 0 1 2900.1 3 1 1 2900.1 4 0 2 2900.1 5 1 2 2900.1 6 0 3 2900.1 7 1 3 2900.1 8 0 4 2900.1 9 1 4 2900.1 10 0 5 2900.1 11 1 5 2900.1 12 0 0 2900.1 13 1 0 2900.1 14 0 1 2900.1 15 1 1 2900.1 16 0 2 2900.1 17 1 2 2900.1 18 0 3 2900.1 19 1 3 2900.1 20 0 4 2900.1 21 1 4 2900.1 22 0 5 2900.1 23 1 5 2900.1 Simulating `input.scs' on icslsrv3.ee.ucla.edu at 7:01:22 PM, Tue Dec 16, 2014 (process id: 21797). Current working directory: /w/ee.00/abidi/qnehal/simulation/CELL28_TIA_Sec_Order/tb_CLK_16PH_Weight_Recomb/adexl/results/data/Interactive.6/1/CELL28_TIA_Sec_Order:tb_CLK_16PH_Weight_Recomb:1/netlist. Command line: /w/apps3/Cadence/MMSIM111/tools.lnx86/spectre/bin/64bit/spectre \ input.scs +escchars +log ../psf/spectre.out -format psfxl -raw \ ../psf +lqtimeout 900 -maxw 5 -maxn 5 +error +info Loading /w/apps3/Cadence/MMSIM111/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... Loading /w/apps3/Cadence/MMSIM111/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ... Loading /w/apps3/Cadence/MMSIM111/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ... Loading /w/apps3/Cadence/MMSIM111/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ... Time for NDB Parsing: CPU = 1.38379 s, elapsed = 1.53579 s. Time accumulated: CPU = 1.38379 s, elapsed = 1.53579 s. Peak resident memory used = 60.1 Mbytes. Created directory input.ahdlSimDB/ (775) Created directory input.ahdlSimDB//3287_N28_MyVerilogA_QN_CLK_16PH_Weight_Recomb_veriloga_veriloga.va.CLK_16PH_Weight_Recomb.ahdlcmi/ (775) Created directory input.ahdlSimDB//3287_N28_MyVerilogA_QN_CLK_16PH_Weight_Recomb_veriloga_veriloga.va.CLK_16PH_Weight_Recomb.ahdlcmi/Linux-64/ (775) Compiling ahdlcmi module library. Finished compilation in 1.12 s (elapsed). Installed compiled interface for CLK_16PH_Weight_Recomb. Opening directory input.ahdlSimDB/ (775) Created directory input.ahdlSimDB//4249_artist_ahdlLib_adder_veriloga_veriloga.va.adder.ahdlcmi/ (775) Created directory input.ahdlSimDB//4249_artist_ahdlLib_adder_veriloga_veriloga.va.adder.ahdlcmi/Linux-64/ (775) Compiling ahdlcmi module library. Finished compilation in 937 ms (elapsed). Installed compiled interface for adder. Time for Elaboration: CPU = 144.978 ms, elapsed = 2.34398 s. Time accumulated: CPU = 1.52877 s, elapsed = 3.88004 s. Peak resident memory used = 69.4 Mbytes. Time for EDB Visiting: CPU = 7.999 ms, elapsed = 15.5561 ms. Time accumulated: CPU = 1.53676 s, elapsed = 3.8959 s. Peak resident memory used = 69.6 Mbytes.