From:	Nhumai T Le <e373035@sbfsr072367.orl.lmco.com>
Sent:	Wednesday, June 26, 2019 3:44 PM
To:	Le, Nhumai T (US)

*This command is used to match the input and output vector syntax between VCD file and spice netlist.
*syntax: .alias VCD_bus_syntax signal_bus_syntax

.alias ra[*] ra<*>


*scope to take care of signals present in lower level hierarchy.In this testcase i have just placed 
buffertest as it contains top-level signals.

.scope tb_digleft_asic 

* .in, .out and .bi are used to define specified bus as input,output and bi-directional signals as is netlist.

.in clr prstsh ra[10:0] row_valid vrefl_m

*These parameters define used when you to converting digital vector to analog signal.
*These specify the rise time, fall time, logical input high, logical input low,logic output high, logic output 
low.
.trise  100
.tfall  100
.vih    3.3 
.vil    0.0
.voh    3.3 
.vol    0.0

*This sets the reference to time t=0 (where you grabbed the VCD signals from) .tdelay 0



*in addition to this if you have specified output vectors in VCD file then you need to "chkwindow" 
parameter to check output signal in the specified window range.