#! tvf namespace import tvf::* VERBATIM { MASK SVDB DIRECTORY svdb QUERY CCI /* ############################################################################################### # # GLOBALFOUNDRIES Singapore Pte. Ltd. # # File: cmos55lpe.lvs.cal # Description: Mentor Calibre LVS Runset for CMOS55LPE/RF Process # Document ID: EDA-CAD-55N-LV035 # Document Revision: 15 # Author: Raju Mani # Date: 2016-07-31 21:32:43 # ############################################################################################### # Copyright (c) 2016 GLOBALFOUNDRIES Singapore Pte. Ltd. ############################################################################################### # This document is confidential and a proprietary product of GLOBALFOUNDRIES Singapore Pte. Ltd. # Any unauthorized use, reproduction or transfer of this document is strictly prohibited. ############################################################################################### # Disclaimer: # ----------- # The information contained herein is confidential and is the property of GLOBALFOUNDRIES and/or # its licensors. GLOBALFOUNDRIES reserves all proprietary, design, manufacturing, reproduction, # use, sales and other rights in the information herein, in its products and services, and to any # article or process utilizing such information, except to the extent that rights are expressly # granted to others. # This document is for informational purposes only, is current only as of the date of publication # and is subject to change by GLOBALFOUNDRIES at any time without notice. While precautions have # been taken in the preparation of the information herein, it may contain technical inaccuracies, # omissions and typographical errors. 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Unless otherwise indicated, all rights reserved. # Do not copy or redistribute except as expressly permitted by GLOBALFOUNDRIES. # ############################################################################################### */ } VERBATIM { } VERBATIM { //*******************************************************************// // Header Section // //*******************************************************************// //*******************************************************************// // SWITCHES FOR THIS CALIBRE LVS DECK // //*******************************************************************// //*******************************************************************// // METALLIZATION OPTIONS // //*******************************************************************// // You MUST uncomment ONE metallization option. // For more information see Table 2-7, Preferred Metallization options, in the // Design Manual. // // a = # of 1x Thin layers // b = # of 2x low-K layers // a_bc_de_fg: c = # of 2x FTEOS layers // d = # of 4x low-K layers // e = # of 4x FTEOS layers // f = # of 12x TEOS layers // g = # of 12x FTEOS layers // // Top Metal is always LB. // //*******************************************************************// // Uncomment 1 Metallization Option OR use environmental variable BEOL_STACK //*******************************************************************// // //#DEFINE 5_00_01_00_LB //(M1, M2, M3, M4, M5, EA, LB) //#DEFINE 6_00_01_00_LB //(M1, M2, M3, M4, M5, M6, EA, LB) //#DEFINE 4_02_00_00_LB //(M1, M2, M3, M4, BA, BB, LB) //#DEFINE 5_02_00_00_LB //(M1, M2, M3, M4, M5, BA, BB, LB) //#DEFINE 6_02_00_00_LB //(M1, M2, M3, M4, M5, M6, BA, BB, LB) //#DEFINE 4_00_02_00_LB //(M1, M2, M3, M4, EA, EB, LB) //#DEFINE 5_00_02_00_LB //(M1, M2, M3, M4, M5, EA, EB, LB) //#DEFINE 6_00_02_00_LB //(M1, M2, M3, M4, M5, M6, EA, EB, LB) //RF-Only Metal Options //#DEFINE 5_00_01_10_LB //(M1, M2, M3, M4, M5, EA, OI, LB) //#DEFINE 6_00_01_10_LB //(M1, M2, M3, M4, M5, M6, EA, OI, LB) //#DEFINE 5_00_00_10_LB //(M1, M2, M3, M4, M5, OI, LB) //#DEFINE 5_01_00_10_LB //(M1, M2, M3, M4, M5, BA, OI, LB) //#DEFINE 6_01_00_10_LB //(M1, M2, M3, M4, M5, M6, BA, OI, LB) //Alternative Metal Options //#DEFINE 5_01_00_00_LB //(M1, M2, M3, M4, M5, BA, LB) //#DEFINE 6_01_00_00_LB //(M1, M2, M3, M4, M5, M6, BA, LB) //#DEFINE 7_01_00_00_LB //(M1, M2, M3, M4, M5, M6, M7, BA, LB) } if [ info exists env(INCLUDE_FILE) ] { VERBATIM {INCLUDE $INCLUDE_FILE} } else { # VERBATIM {INCLUDE $TECHDIR/LVS/sample_design.inc.cal} } VERBATIM { #IFDEF $BEOL_STACK 5_00_00_10_LB #DEFINE 5_00_00_10_LB #ELSE #IFDEF $BEOL_STACK 5_00_01_10_LB #DEFINE 5_00_01_10_LB #ELSE #IFDEF $BEOL_STACK 6_00_01_10_LB #DEFINE 6_00_01_10_LB #ELSE #IFDEF $BEOL_STACK 6_00_02_00_LB #DEFINE 6_00_02_00_LB #ELSE #IFDEF $BEOL_STACK 5_00_01_00_LB #DEFINE 5_00_01_00_LB #ELSE #IFDEF $BEOL_STACK 5_00_02_00_LB #DEFINE 5_00_02_00_LB #ELSE #IFDEF $BEOL_STACK 6_00_01_00_LB #DEFINE 6_00_01_00_LB #ELSE #IFDEF $BEOL_STACK 4_00_02_00_LB #DEFINE 4_00_02_00_LB #ELSE #IFDEF $BEOL_STACK 5_02_00_00_LB #DEFINE 5_02_00_00_LB #ELSE #IFDEF $BEOL_STACK 6_02_00_00_LB #DEFINE 6_02_00_00_LB #ELSE #IFDEF $BEOL_STACK 4_02_00_00_LB #DEFINE 4_02_00_00_LB #ELSE #IFDEF $BEOL_STACK 5_01_00_10_LB #DEFINE 5_01_00_10_LB #ELSE #IFDEF $BEOL_STACK 6_01_00_10_LB #DEFINE 6_01_00_10_LB #ELSE #IFDEF $BEOL_STACK 5_01_00_00_LB #DEFINE 5_01_00_00_LB #ELSE #IFDEF $BEOL_STACK 6_01_00_00_LB #DEFINE 6_01_00_00_LB #ELSE #IFDEF $BEOL_STACK 7_01_00_00_LB #DEFINE 7_01_00_00_LB #ELSE SVRF ERROR "\n\n\n\t _____NO_VALID_METAL_STACK_OPTION_DEFINED_____ \n\n\n \t\t Valid options for BEOL_STACK are: \n\n \t\t\t 5_00_01_10_LB \n\n \t\t\t 5_00_00_10_LB \n\n \t\t\t 6_00_02_00_LB \n\n \t\t\t 5_00_01_00_LB \n\n \t\t\t 5_00_02_00_LB \n\n \t\t\t 6_00_01_00_LB \n\n \t\t\t 4_00_02_00_LB \n\n \t\t\t 5_02_00_00_LB \n\n \t\t\t 4_03_00_00_LB \n\n \t\t\t 6_02_00_00_LB \n\n \t\t\t 4_02_00_00_LB \n\n \t\t\t 5_01_00_10_LB \n\n \t\t\t 6_01_00_10_LB \n\n \t\t\t 5_01_00_00_LB \n\n \t\t\t 6_01_00_00_LB \n\n \t\t\t 7_01_00_00_LB \n\n " #ENDIF // 7_01_00_00_LB #ENDIF // 6_01_00_00_LB #ENDIF // 5_01_00_00_LB #ENDIF // 6_01_00_10_LB #ENDIF // 5_01_00_10_LB #ENDIF // 4_02_00_00_LB #ENDIF // 6_02_00_00_LB #ENDIF // 5_02_00_00_LB #ENDIF // 4_00_02_00_LB #ENDIF // 6_00_01_00_LB #ENDIF // 5_00_02_00_LB #ENDIF // 5_00_01_00_LB #ENDIF // 6_00_02_00_LB #ENDIF // 6_00_01_10_LB #ENDIF // 5_00_01_10_LB #ENDIF // 5_00_00_10_LB } VERBATIM { //*******************************************************************// //*******************************************************************// // SWITCHES - see documentation for description and proper usage // //*******************************************************************// //////////////////////////////////////////////////////////////////// // Custom Switches // //////////////////////////////////////////////////////////////////// // ***NOTE: Refer to the Calibre LVS release notes to learn how to // set these new environmental variables.*** //////////////////////////////////////////////////////////////////// //*******************************************************************// // // // This option is used to not compare device properties. // Uncomment this option if you do not want property comparison. // Be careful using this. // //====================================== // If environmental variables are being // used, do NOT edit the next lines! //====================================== // // To enable/disable this switch please use the following // environmental variable: // // $NO_TRACE_PROPERTY = TRUE/FALSE // //====================================== // If environmental variables are being // used, do NOT edit the next lines! //====================================== //#DEFINE NO_TRACE_PROPERTY // #IFDEF $NO_TRACE_PROPERTY TRUE #DEFINE NO_TRACE_PROPERTY #ENDIF // This option is used to NOT compare FET nf property. // Use this option if you do not want nf property comparison. // Be carefull using this. // // To enable/disable this switch please use the following // environmental variable: // // $CHECK_NUMBER_OF_FINGERS = TRUE/FALSE // //====================================== // If environmental variables are being // used, do NOT edit the next lines! //====================================== //#DEFINE IGNORE_NF_PARAM // #IFDEF $CHECK_NUMBER_OF_FINGERS FALSE #DEFINE IGNORE_NF_PARAM #ENDIF //*******************************************************************// // This option is used to compare TIEDOWN DIODES tdndsx/tdpdnw // Area and Perimeter properties. // Use this option if you want A and perim property comparison. . // // To enable/disable this switch please use the following // environmental variable: // // $CHECK_TIEDOWN_PARAM = TRUE // //====================================== // If environmental variables are being // used, do NOT edit the next lines! //====================================== //#DEFINE CHECK_TIEDOWN_PARAM // #IFDEF $CHECK_TIEDOWN_PARAM TRUE #DEFINE CHECK_TIEDOWN_PARAM #ENDIF // //*******************************************************************// // This option is used not to compare pccrit property of FETs or not. // // To enable/disable this switch please use the following // environmental variable: // // $IGNORE_PCCRIT_PARAM = TRUE/FALSE // //====================================== // If environmental variables are being // used, do NOT edit the next lines! //====================================== // Hardcoded to TRUE because pccrit is not supported in the technology. #DEFINE IGNORE_PCCRIT_PARAM // #IFDEF $IGNORE_PCCRIT_PARAM TRUE #DEFINE IGNORE_PCCRIT_PARAM #ENDIF //*******************************************************************// // // To run PEX, define "PEX_RUN" // To run LVS, do not define "PEX_RUN" // // To enable/disable this switch please use the following // environmental variable: // // $PEX_RUN = TRUE/FALSE // //====================================== // If environmental variables are being // used, do NOT edit the next lines! //====================================== //#DEFINE PEX_RUN // #IFDEF $PEX_RUN TRUE #DEFINE PEX_RUN #IFDEF $CORNERROUNDING TRUE #DEFINE CORNERROUNDING // corner rounding is only valid when PEX_RUN is set to TRUE #ENDIF #ENDIF //*******************************************************************// // // To run ERC, define "ERC_RUN" // // $ERC_RUN = TRUE/FALSE // //====================================== // If environmental variables are being // used, do NOT edit the next lines! //====================================== //#DEFINE ERC_RUN // #IFDEF $ERC_RUN TRUE #DEFINE ERC_RUN #ENDIF //*******************************************************************// // // Series MOS reduction is not permitted by Default // Uncomment the switch below if user wants to reduce sreies MOS devices // // To enable/disable this switch please use the following // environmental variable: // // $REDUCE_SERIES_MOS = TRUE/FALSE // //====================================== // If environmental variables are being // used, do NOT edit the next lines! //====================================== // //#DEFINE REDUCE_SERIES_MOS // #IFDEF $REDUCE_SERIES_MOS TRUE #DEFINE REDUCE_SERIES_MOS #ENDIF //*******************************************************************// // // Split gate MOS reduction is not permitted by Default // Uncomment the switch below if user wants to reduce sreies MOS devices // // To enable/disable this switch please use the following // environmental variable: // // $REDUCE_SPLIT_GATES = TRUE/FALSE // //====================================== // If environmental variables are being // used, do NOT edit the next lines! //====================================== // //#DEFINE REDUCE_SPLIT_GATES // #IFDEF $REDUCE_SPLIT_GATES TRUE #DEFINE REDUCE_SPLIT_GATES #ENDIF //*******************************************************************// // // LVS recognize RX FILL as RX drawing by default. // Uncomment the switch below if user wants to exclude RX FILL as drawing // // To enable/disable this switch please use the following // environmental variable: // // $EXCLUDE_RX_FILL = TRUE/FALSE // //====================================== // If environmental variables are being // used, do NOT edit the next lines! //====================================== // //#DEFINE EXCLUDE_RX_FILL // #IFDEF $EXCLUDE_RX_FILL TRUE #DEFINE EXCLUDE_RX_FILL #ENDIF //*******************************************************************// // // By default,LVS use 2K high-Rs p+ poly resistor // To define 1K p+ poly resistor,please use the following environmental variable: // // $POLY_HIGH_RES = [1K || 2K] // // e.g. // setenv POLY_HIGH_RES 1K # [1K || 2K] // //========================================================================================================// // If environmental variables are being used, do NOT edit the next lines! // //========================================================================================================// // #DEFINE POLY_HIGH_RES_1K // Uncomment this line to extract 1K p+ poly resistor // #IFDEF $POLY_HIGH_RES 1K #DEFINE POLY_HIGH_RES_1K #ENDIF // $POLY_HIGH_RES // //*******************************************************************// //*******************************************************************// // Include files // //*******************************************************************// // General calibre tool options which users are required to set have // been move to design include file, please use $INCLUDE_FILE to locate // user include file, by default sample_design.inc.cal will be included. // INCLUDE $TECHDIR/LVS/sample_design.inc.cal #IFDEF $TECHDIR #ENDIF } VERBATIM { //*******************************************************************// // Description Section // //*******************************************************************// //INCLUDE $TECHDIR/LVS/Include/cmos55lpe.extract.cal_ind //INCLUDE $TECHDIR/LVS/Include/cmos55lpe.layers.cal_ind INCLUDE $TECHDIR/LVS/Include/cmos55lpe.extract.cal INCLUDE $TECHDIR/LVS/Include/cmos55lpe.compare.cal INCLUDE $TECHDIR/LVS/Include/cmos55lpe.layers.cal LVS FILTER D(diodepwtw) OPEN LVS FILTER D(diodetwx) OPEN LVS FILTER D(diodenwx) OPEN LVS FILTER D(diodenx) OPEN LVS FILTER D(diodepnw) OPEN LVS FILTER D(diodedgnx) OPEN LVS FILTER D(diodedgpnw) OPEN LVS FILTER D(diodehvpwtw) OPEN LVS FILTER D(diodeisotwx) OPEN LVS SOFTCHK nband CONTACT LVS SOFTCHK psub CONTACT LVS SOFTCHK nw_no_n3 CONTACT LVS SOFTCHK nw_n3_t3 CONTACT #IFDEF ERC_RUN ERC SELECT CHECK FLOATING_CHKs #ENDIF ERC RESULTS DATABASE "./ERC_results.asc" ERC SUMMARY REPORT "./ERC_results.rep" //*******************************************************************// // SET Series & Parallel STATEMENTS // //*******************************************************************// #IFNDEF REDUCE_SPLIT_GATES LVS REDUCE SPLIT GATES NO #ENDIF LVS REDUCE SEMI SERIES MOS NO //YES LVS REDUCE SERIES MOS NO //YES LVS REDUCE PARALLEL BIPOLAR YES //YES LVS REDUCE PARALLEL CAPACITORS YES //YES LVS REDUCE PARALLEL DIODES YES //YES LVS REDUCE PARALLEL MOS YES //YES LVS REDUCE PARALLEL RESISTORS YES //YES LVS REDUCE SERIES CAPACITORS YES //YES LVS REDUCE SERIES RESISTORS YES //YES LVS REDUCE D(tdpdnw) PARALLEL YES LVS REDUCE D(tdndsx) PARALLEL YES LVS REDUCE D(tddgpdnw) PARALLEL YES LVS REDUCE D(tddgndsx) PARALLEL YES //*******************************************************************// // END SET REDUCE STATEMENTS // //*******************************************************************// //*******************************************************************// // Set TRACE Tolerances - Do Not Change // //*******************************************************************// VARIABLE trace_hg 2.5e-9 VARIABLE trace_int 0.5 VARIABLE trace_area 1e-15 //*******************************************************************// // End of Header Section // //*******************************************************************// //********************************************************************// // END OF FILE // //********************************************************************// }