// VerilogA for behavioral_blocks, test_parent, veriloga

`include "constants.vams"
`include "disciplines.vams"

module test_parent(in, out);
input in;
output out;

parameter integer N = 9	from [0:inf);

genvar i;

electrical in, out;

generate

	for (i = 0; i < N; i = i+1) begin
		test1 I_TEST1 (in,out);
		test2 I_TEST2 (in,out);
	end

endgenerate

endmodule