// Point Netlist Generated on: Aug  2 14:51:54 2022
// Generated for: spectre
// Design Netlist Generated on: Aug  2 14:51:54 2022
// Design library name: sdd5e_TB
// Design cell name: test_pulse_gen
// Design view name: schematic
simulator lang=spectre
global 0
parameters vpulse_mV=500 cload_pf=5 pulse_width_ns=12 ttran_ns=0.1 \
    vdda_val=0.8 vthreshold_mV=250 period_vpulse_ns=50
include "$CDS_WORKAREA/src/simCases/apdser_spectre_model.scs" section=typicalmid
parameters  sorting_num=1e9 area_predictn_core=1e7 area_predictp_core=1e7 \
    area_predictn_io=1e6 area_predictp_io=1e6

// Library name: sdd5e_TB
// Cell name: test_pulse_gen
// View name: schematic
V0 (vin vssa) vsource type=pwl wave=[ 0 0 1n 0 \
        ((1+period_vpulse_ns/2)*1e-09/2) (vpulse_mV*1e-03) \
        ((5+1+period_vpulse_ns/2)*1e-09) (vpulse_mV*1e-03) \
        ((10+5+1+period_vpulse_ns/2)*1e-09) (vpulse_mV*1e-03) \
        ((10+5+1+period_vpulse_ns)*1e-09) 0 ]
pulse_gen (vcomp_out vout) single_shot pulse_width=pulse_width_ns*1e-09 \
        vlogic_high=vdda_val vlogic_low=0 vtrans=vdda_val/2 \
        tdel=5*ttran_ns*1e-09 trise=ttran_ns*1e-09 tfall=ttran_ns*1e-09
comparator (vin vref vcomp_out) comparator sigout_high=vdda_val \
        sigout_low=0 sigin_offset=0 comp_slope=-1e9
V2 (vssa 0) vsource dc=0 type=dc
V1 (vref vssa) vsource dc=vthreshold_mV*1e-03 type=dc
C0 (vout vssa) capacitor c=cload_pf*1e-12
simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=25 tnom=25 scalem=1.0 gmin=1e-12 rforce=1 \
    nportirfiledir="/project/sdd5e/users/smlogan/cds/.cadence/mmsim" \
    maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
    sensfile="../psf/sens.output" checklimitdest=psf \
    disk_check_autoresume=yes 
tran tran stop=100n errpreset=moderate write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5 \
    saveperiodhistory=yes 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save vin vref vcomp_out vout vssa 
saveOptions options save=selected subcktoppoint=yes
ahdl_include "/tools/virtuoso/20.1.ISR26/tools/dfII/samples/artist/ahdlLib/single_shot/veriloga/veriloga.va"
ahdl_include "/tools/virtuoso/20.1.ISR26/tools/dfII/samples/artist/ahdlLib/comparator/veriloga/veriloga.va"