`include "discipline.h"
`include "constants.h"

// $Date: 1998/09/23 03:13:33 $
// $Revision: 1.2 $
//
//
// Based on the OVI Verilog-A Language Reference Manual, version 1.0 1996
//
//



//--------------------
// and
//
// -  and gate
//
// vin1, vin2:	[V,A]
// vout:	[V,A]
//
// INSTANCE parameters
//    vlogic_high = output voltage for high [V]
//    vlogic_low  = output voltage for high [V]
//    vtrans      = voltages above this at input are considered high [V]
//    tdel, trise, tfall = {usual} [s]
//

module and_gate(vin1, vin2, vout);
input vin1, vin2;
output vout;
electrical vin1, vin2, vout;
parameter real vlogic_high = 5;
parameter real vlogic_low = 0;
parameter real vtrans = 1.4;
parameter real tdel = 2u from [0:inf);
parameter real trise = 1u from (0:inf);
parameter real tfall = 1u from (0:inf);

   real vout_val;
   integer logic1, logic2;


   analog begin

      @ ( initial_step ) begin
	 if (vlogic_high < vlogic_low) begin
	    $display("Range specification error.  vlogic_high = (%E) less than vlogic_low = (%E).\n", vlogic_high, vlogic_low );
	    $finish;
	 end
	 if (vtrans > vlogic_high || vtrans < vlogic_low) begin
	    $display("Inconsistent $threshold specification w/logic family.\n");
	 end
      end

      logic1 = V(vin1) > vtrans;
      logic2 = V(vin2) > vtrans;

      @ (cross(V(vin1) - vtrans, 1))  logic1 = 1;
      @ (cross(V(vin1) - vtrans, -1)) logic1 = 0;

      @ (cross(V(vin2) - vtrans, 1))  logic2 = 1;
      @ (cross(V(vin2) - vtrans, -1)) logic2 = 0;

      //
      // define the logic function.
      //
      vout_val = (logic1 && logic2) ? vlogic_high : vlogic_low;

      V(vout) <+ transition( vout_val, tdel, trise, tfall);
   end
endmodule