// VerilogA for , verloga

`include "constants.vams"
`include "disciplines.vams"

module flash_nbit_pre_amp( inp, inn, clk, out );
parameter real FS=2;
parameter integer nlevel=7;  //input threshold level
parameter real gain=1;


input inp, inn;
input clk;
output  [nlevel:0]out;


electrical inp, inn,clk;
electrical [nlevel:0]out;



real LSB=FS/nlevel;
real td=0;
real tt=0;
real vdd=1.1;
real vth=vdd/2;
real dir=1;
real Vref_i=0;
real sample;
genvar i;
real result[nlevel:0];




analog begin
	@(cross(V(clk)-vth, +1) or initial_step) begin	
		sample = gain*(V(inp)-V(inn));
		for (i = nlevel; i >= 0; i =i -1) begin
			Vref_i=FS/2-LSB/2-(nlevel-i)*LSB;
			if (sample > Vref_i) begin
				 result[i] = vdd;
			end 
			else begin
			result[i] = 0;
			end 
		end	
	end
	for (i = nlevel; i >=0; i = i - 1) begin
		V(out[i])<+ transition(result[i], td, tt);
	end
end

endmodule