// Verilog-AMS cds_globals module for top-level cell:
//    testcases/tb_testcase_ams_include_vars.
// Generated by ADE.
// Cadence Design Systems, Inc.

// This is an autoGenerated file, any changes done to this file may get lost.

`include "disciplines.vams"
`include "userDisciplines.vams"

module cds_globals;

// Global Signals
   electrical \gnd! ;
   ground \gnd! ;

// Design Variables
   dynamicparam real temperature = 27;
   dynamicparam real test_val_gui = 10;
   dynamicparam real clk_f = 1G;

endmodule