// Point Netlist Generated on: Oct  6 10:21:05 2025
// Generated for: spectre
// Design Netlist Generated on: Oct  6 10:21:05 2025
// Design library name: testcases
// Design cell name: tb_testcase_ams_include_vars
// Design view name: config
simulator lang=spectre
include "ade_e.scs"
global 0
parameters test_val_file temperature=27 test_val_gui=10 clk_f=1G
include "/Project_Path/ProjectX/cadence/my_vars.scs"

// Library name: testcases
// Cell name: tb_testcase_ams_include_vars
// View name: schematic
// Inherited view list: spectre spice pspice verilog verilogams
// behavioral functional systemVerilog schematic veriloga vhdl vhdlams
// wreal
V0 (clk 0) vsource dc=1 type=pulse val0=0 val1=1 period=1/clk_f \
        delay=-(1p)/2 rise=1p fall=(1p) width=0.5*(1/clk_f-(1p)-((1p)))
I0 (clk out_gui out_file) testcase_veriloga test_var_gui=test_val_gui \
        test_var_file=test_val_file
simulatorOptions options psfversion="1.4.0" temp=27 tnom=27 scalem=1.0 \
    scale=1.0 gmin=1e-12 rforce=1 redefinedparams=warning maxnotes=5 \
    maxwarns=5 digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=sqldb 
tran tran stop=3n write="spectre.ic" writefinal="spectre.fc" \
    annotate=status 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub
ahdl_include "/Project_Path/ProjectX/cadence/testcases/testcase_veriloga/veriloga/veriloga.va"