`include "constants.vams"
`include "disciplines.vams"

module testcase_veriloga(clk, out_gui, out_file);

input clk;
output out_gui, out_file;
electrical clk, out_gui, out_file;

parameter real test_var_gui = 0;
parameter real test_var_file = 0;

analog begin

@(initial_step) begin
$display("Testcase VerilogA %M: variable test_var_gui value passed is %f", test_var_gui);
$display("Testcase VerilogA %M: variable test_var_file value passed is %f", test_var_file);
end
V(out_gui) <+ transition(test_var_gui, 0, 1p, 1p);
V(out_file) <+ transition(test_var_file, 0, 1p, 1p);
end


endmodule