// VerilogA for simple transient compatible eightbit_ad,
// sml 8/10/2020


`include "constants.vams"
`include "disciplines.vams"

module eightbit_ad(VOUT, VDD, VIN, VSS);
output [7:0] VOUT;
electrical [7:0] VOUT;
input VDD;
electrical VDD;
input VIN;
electrical VIN;
input VSS;
electrical VSS;
integer vin_integer;
parameter real rise_fall_time = 50e-12;
integer vout[7:0];

   analog begin
   
   vin_integer = V(VIN,VSS);

   if (vin_integer%256<128) V(VOUT[7],VSS)<+V(VSS);
      else V(VOUT[7],VSS)<+V(VDD,VSS);   
   V(VOUT[7],VSS)<+ transition(V(VDD)*vout[7],rise_fall_time,rise_fall_time);

   if (vin_integer%128<64) V(VOUT[6],VSS)<+V(VSS);
      else V(VOUT[6],VSS)<+V(VDD,VSS);   
   V(VOUT[6],VSS)<+ transition(V(VDD)*vout[6],rise_fall_time,rise_fall_time);

   if (vin_integer%64<32) V(VOUT[5],VSS)<+V(VSS);
      else V(VOUT[5],VSS)<+V(VDD,VSS);   
   V(VOUT[5],VSS)<+ transition(V(VDD)*vout[5],rise_fall_time,rise_fall_time);

   if (vin_integer%32<16) V(VOUT[4],VSS)<+V(VSS);
      else V(VOUT[4],VSS)<+V(VDD,VSS);   
   V(VOUT[4],VSS)<+ transition(V(VDD)*vout[4],rise_fall_time,rise_fall_time);
   
   if (vin_integer%16<8) V(VOUT[3],VSS)<+V(VSS);
      else V(VOUT[3],VSS)<+V(VDD,VSS);   
   V(VOUT[3],VSS)<+ transition(V(VDD)*vout[3],rise_fall_time,rise_fall_time);

   if (vin_integer%8<4) V(VOUT[2],VSS)<+V(VSS);
      else V(VOUT[2],VSS)<+V(VDD,VSS);   
   V(VOUT[2],VSS)<+ transition(V(VDD)*vout[2],rise_fall_time,rise_fall_time);

   if (vin_integer%4<2) vout[1]=0;
      else vout[1]=1;
   V(VOUT[1],VSS)<+ transition(V(VDD)*vout[1],rise_fall_time,rise_fall_time);

   if (vin_integer%2<1) vout[0]=0;
      else vout[0]=1;
   V(VOUT[0],VSS)<+ transition(V(VDD)*vout[0],rise_fall_time,rise_fall_time);
   
   end
   
endmodule