////////////////////////////////////////////////////////////////////////
// PLEASE DO NOT EDIT OR COMPILE THIS FILE.                             
// IT IS MEANT FOR VIEWING PURPOSE ONLY.                                
// 
// All files for configuration: (INVERTER_FF Test_ckt config)
////////////////////////////////////////////////////////////////////////

// AMS netlist generated by the OSS based AMS netlister
// IC subversion:  IC6.1.5.500.17 
// IUS version: 12.20-s038
// Copyright(C) 2005-2009, Cadence Design Systems, Inc
// User: ankit_soc Pid: 23986
// Design library name: INVERTER_FF
// Design cell name: Test_ckt
// Design view name: config
// Solver: Spectre

`include "disciplines.vams"
`include "userDisciplines.vams"
// Library - INVERTER_FF, Cell - ams_inv_ff, View - schematic
// LAST TIME SAVED: Apr 15 00:08:13 2015
// NETLIST TIME: Apr 15 01:00:11 2015
`timescale 1ns / 1ns 

(* cds_ams_schematic *) 
module ams_inv_ff (OUT, VDD, VSS, CLOCK, RESET, Vin);

output  OUT;

inout  VDD, VSS;

input  CLOCK, RESET, Vin;


p_18_mm #(.w(1u), .l(500n), .nf(1), .mis_flag(1), .ad(4.9e-13), 
    .as(4.9e-13), .pd(2.98u), .ps(2.98u), .m("(1)*(1)"), 
    .mf("(1)*(1)")) 
(* integer passed_mfactor = "m"; *)
M0 (net16, Vin, VDD, VDD);

n_18_mm #(.w(2u), .l(500n), .nf(1), .mis_flag(1), .ad(9.8e-13), 
    .as(9.8e-13), .pd(4.98u), .ps(4.98u), .m("(1)*(1)"), 
    .mf("(1)*(1)")) 
(* integer passed_mfactor = "m"; *)
M1 (net16, Vin, VSS, VSS);

d_ff I0 ( .q(OUT), .clk(CLOCK), .data(net16), .reset(RESET));

endmodule
// Library - INVERTER_FF, Cell - Test_ckt, View - schematic
// LAST TIME SAVED: Apr 15 00:56:34 2015
// NETLIST TIME: Apr 15 01:00:11 2015
`timescale 1ns / 1ns 

(* cds_ams_schematic *) 
module Test_ckt ();


ams_inv_ff I0 ( .VSS(cds_globals.\gnd! ), .VDD(VDD), .OUT(OUT), 
    .CLOCK(CLOCK), .RESET(RESET), .Vin(DATA));

vsource #(.type("pulse"), .val0(1.8), .val1(0), .period(1m), 
    .width(100u)) V2 (RESET, cds_globals.\gnd! );

vsource #(.type("pulse"), .val0(0), .val1(1.8), .period(4u), 
    .width(2.5u)) V1 (DATA, cds_globals.\gnd! );

vsource #(.type("pulse"), .val0(0), .val1(1.8), .period(1u), 
    .rise(10.00n), .fall(10.00n), .width(500.0n)) V0 (CLOCK, 
    cds_globals.\gnd! );

vsource #(.dc(1.8), .type("dc")) V3 (VDD, cds_globals.\gnd! );

endmodule
// Verilog-AMS cds_globals module for top-level cell:
//    INVERTER_FF/Test_ckt.
// Generated by ADE.
// Cadence Design Systems, Inc.

// This is an autoGenerated file, any changes done to this file may get lost.

`include "disciplines.vams"
`include "userDisciplines.vams"

module cds_globals;

// Global Signals
   electrical \gnd! ;
   ground \gnd! ;

// Design Variables

endmodule

// This is the Cadence AMS Designer(R) analog simulation control file. 
// It specifies the options and analyses for the Spectre analog solver. 

simulator lang=spectre 

simulatorOptions options temp=27 tnom=27 scale=1.0 scalem=1.0 reltol=1e-3 \
vabstol=1e-6 iabstol=1e-12 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 pivrel=1e-3 checklimitdest=psf 

dcOpInfo info what=oppoint where=rawfile writedc="dcOp" 

tran tran stop=40u errpreset=moderate save=none write="spectre.ic" \
writefinal="spectre.fc" annotate=status maxiters=5 

finalTimeOP info what=oppoint where=rawfile

modelParameter info what=models where=rawfile 
element info what=inst where=rawfile 
outputParameter info what=output where=rawfile 

# This is the NC-SIM(R) probe command file
# used in the AMS-ADE integration.


#
# Database settings
#
if { [info exists ::env(AMS_RESULTS_DIR) ] } { set AMS_RESULTS_DIR $env(AMS_RESULTS_DIR)} else {set AMS_RESULTS_DIR "../psf"}
database -open ams_database -into ${AMS_RESULTS_DIR} -default

#
# Probe settings
#